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170 lines
6.8 KiB
VHDL
170 lines
6.8 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all ;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity fuq_lza_ej is port(
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effsub :in std_ulogic;
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sum :in std_ulogic_vector(0 to 162);
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car :in std_ulogic_vector(53 to 162);
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lzo_b :in std_ulogic_vector(0 to 162);
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edge :out std_ulogic_vector(0 to 162)
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);
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END fuq_lza_ej;
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-- generic 3 bit edge ::
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-- P G !Z
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-- P Z !G
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-- !P G !G
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-- !P Z !Z
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ARCHITECTURE fuq_lza_ej OF fuq_lza_ej IS
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal x0, x1, x2 :std_ulogic_vector(0 to 52);
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signal x1_b, ej_b :std_ulogic_vector(0 to 52);
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signal g_b, z, p, g, z_b, p_b :std_ulogic_vector(53 to 162);
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signal sum_52_b :std_ulogic;
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signal lzo_54 :std_ulogic;
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signal gz, zg, gg, zz :std_ulogic_vector(55 to 162);
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signal e0_b, e1_b :std_ulogic_vector(53 to 162);
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signal e2_b : std_ulogic_vector(54 to 54);
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signal unused :std_ulogic ;
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BEGIN
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unused <= g(54) or z_b(53) or z_b(162) or p_b(161) or p_b(162) ;
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---------------------------------------------
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-- (0:52) only one data input
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---------------------------------------------
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x0(0 to 52) <= tidn & effsub & sum(0 to 50); -- just a rename
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x1(0 to 52) <= effsub & sum(0 to 51); -- just a rename
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x2(0 to 52) <= sum(0 to 52); -- just a rename
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xb_00: x1_b(0 to 52) <= not x1(0 to 52) ;
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ejx_00: ej_b(0 to 52) <= not( x1_b(0 to 52) and ( x0(0 to 52) or x2(0 to 52) ) );
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ej_00: edge(0 to 52) <= not( ej_b(0 to 52) and lzo_b(0 to 52) );
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-------------------------------------------------------------------
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-- (53) psuedo bit
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-------------------------------------------------------------------
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glo_53: g_b(53) <= not( sum(53) and car(53) );
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zhi_53: z (53) <= not( sum(53) or car(53) );
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phi_53: p (53) <= ( sum(53) xor car(53) );
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ghi_53: g (53) <= not( g_b(53) );
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zlo_53: z_b(53) <= not( z (53) );--UNUSED
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plo_53: p_b(53) <= not( p (53) );
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s52_53: sum_52_b <= not( sum(52) );
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e0_53: e0_b(53) <= not( sum(51) and sum_52_b );
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e1_53: e1_b(53) <= not( sum_52_b and g(53) );
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ej_53: edge(53) <= not( lzo_b(53) and e0_b(53) and e1_b(53) ); --output
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-------------------------------------------------------------------
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-- (54) pseudo bit + 1
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-------------------------------------------------------------------
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glo_54: g_b(54) <= not( sum(54) and car(54) );
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zhi_54: z (54) <= not( sum(54) or car(54) );
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phi_54: p (54) <= ( sum(54) xor car(54) );
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ghi_54: g (54) <= not( g_b(54) );--UNUSED
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zlo_54: z_b(54) <= not( z (54) );
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plo_54: p_b(54) <= not( p (54) );
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zb_54: lzo_54 <= not lzo_b(54);
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e0_54: e0_b(54) <= not( sum_52_b and p(53) and z_b(54) ); --really is p54 (demotes to z54)
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e1_54: e1_b(54) <= not( sum(52) and p(53) and g_b(54) ); --really is p54 (demotes to z54)
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e2_54: e2_b(54) <= not( (sum(52) and z(53) ) or lzo_54 );
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ej_54: edge(54) <= not( e0_b(54) and e1_b(54) and e2_b(54) ); --output
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-------------------------------------------------------------------
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-- (55) pseudo bit + 2
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-------------------------------------------------------------------
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glo_55: g_b(55) <= not( sum(55) and car(55) );
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zhi_55: z (55) <= not( sum(55) or car(55) );
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phi_55: p (55) <= ( sum(55) xor car(55) );
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ghi_55: g (55) <= not( g_b(55) );
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zlo_55: z_b(55) <= not( z (55) );
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plo_55: p_b(55) <= not( p (55) );
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gz_55: gz(55) <= not( g_b(54) or z(55) );
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zg_55: zg(55) <= not( z_b(54) or g(55) );
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gg_55: gg(55) <= not( g_b(54) or g(55) );
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zz_55: zz(55) <= not( z_b(54) or z(55) );
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e1_55: e1_b(55) <= not( p_b(53) and ( gz(55) or zg(55) ) ); -- P is flipped for psuedo bit
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e0_55: e0_b(55) <= not( p (53) and ( gg(55) or zz(55) ) ); -- P is flipped for psuedo bit
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ej_55: edge(55) <= not( e0_b(55) and e1_b(55) and lzo_b(55) ); --output
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-------------------------------------------------------------------
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-- (56:162) normal 2 input edge
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-------------------------------------------------------------------
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glo_56: g_b(56 to 162) <= not( sum(56 to 162) and car(56 to 162) );
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zhi_56: z (56 to 162) <= not( sum(56 to 162) or car(56 to 162) );
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phi_56: p (56 to 162) <= ( sum(56 to 162) xor car(56 to 162) );
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ghi_56: g (56 to 162) <= not( g_b(56 to 162) );
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zlo_56: z_b(56 to 162) <= not( z (56 to 162) );--162 unused
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plo_56: p_b(56 to 162) <= not( p (56 to 162) );--161,162 unused
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gz_56: gz(56 to 162) <= not( g_b(55 to 161) or z(56 to 162) );
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zg_56: zg(56 to 162) <= not( z_b(55 to 161) or g(56 to 162) );
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gg_56: gg(56 to 162) <= not( g_b(55 to 161) or g(56 to 162) );
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zz_56: zz(56 to 162) <= not( z_b(55 to 161) or z(56 to 162) );
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e1_56: e1_b(56 to 162) <= not( p (54 to 160) and ( gz(56 to 162) or zg(56 to 162) ) );
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e0_56: e0_b(56 to 162) <= not( p_b(54 to 160) and ( gg(56 to 162) or zz(56 to 162) ) );
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ej_56: edge(56 to 162) <= not( e0_b(56 to 162) and e1_b(56 to 162) and lzo_b(56 to 162) ); --output
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END; -- ARCH fuq_lza_ej
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