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299 lines
11 KiB
VHDL
299 lines
11 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity fuq_perv is
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generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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pc_fu_sg_3 : in std_ulogic_vector(0 to 1);
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pc_fu_abst_sl_thold_3 : in std_ulogic;
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pc_fu_func_sl_thold_3 : in std_ulogic_vector(0 to 1);
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pc_fu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 1);
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pc_fu_gptr_sl_thold_3 : in std_ulogic;
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pc_fu_time_sl_thold_3 : in std_ulogic;
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pc_fu_ary_nsl_thold_3 : in std_ulogic;
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pc_fu_cfg_sl_thold_3 : in std_ulogic;
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pc_fu_repr_sl_thold_3 : in std_ulogic;
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pc_fu_fce_3 : in std_ulogic;
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tc_ac_ccflush_dc : in std_ulogic;
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tc_ac_scan_diag_dc : in std_ulogic;
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abst_sl_thold_1 : out std_ulogic;
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func_sl_thold_1 : out std_ulogic_vector(0 to 1);
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time_sl_thold_1 : out std_ulogic;
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ary_nsl_thold_1 : out std_ulogic;
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gptr_sl_thold_0 : out std_ulogic;
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cfg_sl_thold_1 : out std_ulogic;
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func_slp_sl_thold_1 : out std_ulogic;
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fce_1 : out std_ulogic;
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sg_1 : out std_ulogic_vector(0 to 1);
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clkoff_dc_b : out std_ulogic;
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act_dis : out std_ulogic;
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delay_lclkr_dc : out std_ulogic_vector(0 to 9);
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mpw1_dc_b : out std_ulogic_vector(0 to 9);
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mpw2_dc_b : out std_ulogic_vector(0 to 1);
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repr_scan_in : in std_ulogic; --tc_ac_repr_scan_in(2)
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repr_scan_out : out std_ulogic; --tc_ac_repr_scan_in(2)
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gptr_scan_in : in std_ulogic;
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gptr_scan_out : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end fuq_perv;
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architecture fuq_perv of fuq_perv is
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signal abst_sl_thold_2 : std_ulogic;
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signal time_sl_thold_2 : std_ulogic;
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signal func_sl_thold_2 : std_ulogic_vector(0 to 1);
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signal gptr_sl_thold_2 : std_ulogic;
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signal ary_nsl_thold_2 : std_ulogic;
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signal cfg_sl_thold_2 : std_ulogic;
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signal repr_sl_thold_2 : std_ulogic;
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signal func_slp_sl_thold_2 : std_ulogic;
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signal sg_2 : std_ulogic_vector(0 to 1);
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signal fce_2 : std_ulogic;
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signal gptr_sl_thold_1 : std_ulogic;
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signal repr_sl_thold_1 : std_ulogic;
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signal sg_1_int : std_ulogic_vector(0 to 1);
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signal gptr_sl_thold_0_int : std_ulogic;
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signal repr_sl_thold_0 : std_ulogic;
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signal repr_sl_force : std_ulogic;
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signal repr_sl_thold_0_b : std_ulogic;
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signal repr_in : std_ulogic;
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signal repr_UNUSED : std_ulogic;
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signal spare_unused : std_ulogic;
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signal sg_0 : std_ulogic;
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signal gptr_sio : std_ulogic;
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signal prv_delay_lclkr_dc : std_ulogic_vector(0 to 9);
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signal prv_mpw1_dc_b : std_ulogic_vector(0 to 9);
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signal prv_mpw2_dc_b : std_ulogic_vector(0 to 1);
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signal prv_act_dis : std_ulogic;
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signal prv_clkoff_dc_b : std_ulogic;
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signal tihi : std_ulogic;
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begin
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tihi <= '1';
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perv_3to2_reg: tri_plat
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generic map (width => 12, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0 to 1) => pc_fu_func_sl_thold_3(0 to 1),
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din(2) => pc_fu_gptr_sl_thold_3,
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din(3) => pc_fu_abst_sl_thold_3,
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din(4 to 5) => pc_fu_sg_3(0 to 1),
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din(6) => pc_fu_time_sl_thold_3,
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din(7) => pc_fu_fce_3,
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din(8) => pc_fu_ary_nsl_thold_3,
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din(9) => pc_fu_cfg_sl_thold_3,
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din(10) => pc_fu_repr_sl_thold_3,
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din(11) => pc_fu_func_slp_sl_thold_3(0),
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q(0 to 1) => func_sl_thold_2(0 to 1),
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q(2) => gptr_sl_thold_2,
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q(3) => abst_sl_thold_2,
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q(4 to 5) => sg_2(0 to 1),
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q(6) => time_sl_thold_2,
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q(7) => fce_2,
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q(8) => ary_nsl_thold_2,
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q(9) => cfg_sl_thold_2,
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q(10) => repr_sl_thold_2,
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q(11) => func_slp_sl_thold_2 );
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perv_2to1_reg: tri_plat
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generic map (width => 12, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0 to 1) => func_sl_thold_2(0 to 1),
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din(2) => gptr_sl_thold_2,
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din(3) => abst_sl_thold_2,
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din(4 to 5) => sg_2(0 to 1),
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din(6) => time_sl_thold_2,
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din(7) => fce_2,
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din(8) => ary_nsl_thold_2,
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din(9) => cfg_sl_thold_2,
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din(10) => repr_sl_thold_2,
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din(11) => func_slp_sl_thold_2,
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q(0 to 1) => func_sl_thold_1(0 to 1),
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q(2) => gptr_sl_thold_1,
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q(3) => abst_sl_thold_1,
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q(4 to 5) => sg_1_int(0 to 1),
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q(6) => time_sl_thold_1,
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q(7) => fce_1,
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q(8) => ary_nsl_thold_1,
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q(9) => cfg_sl_thold_1,
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q(10) => repr_sl_thold_1,
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q(11) => func_slp_sl_thold_1 );
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sg_1(0 to 1) <= sg_1_int(0 to 1);
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perv_1to0_reg: tri_plat
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generic map (width => 3, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => gptr_sl_thold_1,
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din(1) => sg_1_int(0),
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din(2) => repr_sl_thold_1,
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q(0) => gptr_sl_thold_0_int,
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q(1) => sg_0,
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q(2) => repr_sl_thold_0 );
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gptr_sl_thold_0 <= gptr_sl_thold_0_int;
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-- Pipeline mapping of mpw1_b and delay_lclkr, mpw2_b
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-- RF0 8 1
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-- RF1 0 0
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-- EX1 1 0
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-- EX2 2 0
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-- EX3 3 0
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-- EX4 4 0
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-- EX5 5 1
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-- EX6 6 1
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-- EX7 7 1
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-- Ctrl 9 1
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perv_lcbctrl0: tri_lcbcntl_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => sg_0,
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nclk => nclk,
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scan_in => gptr_scan_in,
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scan_diag_dc => tc_ac_scan_diag_dc,
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thold => gptr_sl_thold_0_int,
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clkoff_dc_b => prv_clkoff_dc_b,
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delay_lclkr_dc => prv_delay_lclkr_dc(0 to 4),
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act_dis_dc => open,
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mpw1_dc_b => prv_mpw1_dc_b(0 to 4),
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mpw2_dc_b => prv_mpw2_dc_b(0),
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scan_out => gptr_sio);
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perv_lcbctrl1: tri_lcbcntl_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => sg_0,
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nclk => nclk,
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scan_in => gptr_sio,
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scan_diag_dc => tc_ac_scan_diag_dc,
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thold => gptr_sl_thold_0_int,
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clkoff_dc_b => open,
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delay_lclkr_dc => prv_delay_lclkr_dc(5 to 9),
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act_dis_dc => open,
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mpw1_dc_b => prv_mpw1_dc_b(5 to 9),
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mpw2_dc_b => prv_mpw2_dc_b(1),
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scan_out => gptr_scan_out);
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--Outputs
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delay_lclkr_dc(0 to 9) <= prv_delay_lclkr_dc(0 to 9);
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mpw1_dc_b(0 to 9) <= prv_mpw1_dc_b(0 to 9);
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mpw2_dc_b(0 to 1) <= prv_mpw2_dc_b(0 to 1);
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--never disable act pins, they are used functionally
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prv_act_dis <= '0';
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act_dis <= prv_act_dis;
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clkoff_dc_b <= prv_clkoff_dc_b;
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-- Repower latch for repr scan ins/outs
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repr_sl_lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
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clkoff_b => prv_clkoff_dc_b,
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thold => repr_sl_thold_0,
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sg => sg_0,
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act_dis => prv_act_dis,
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forcee => repr_sl_force,
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thold_b => repr_sl_thold_0_b );
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repr_in <= '0';
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repr_rpwr_lat: tri_rlmreg_p
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generic map (init => 0, expand_type => expand_type, width => 1)
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port map (nclk => nclk,
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act => tihi,
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forcee => repr_sl_force,
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delay_lclkr => prv_delay_lclkr_dc(9),
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mpw1_b => prv_mpw1_dc_b(9),
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mpw2_b => prv_mpw2_dc_b(1),
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thold_b => repr_sl_thold_0_b,
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sg => sg_0,
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vd => vdd,
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gd => gnd,
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scin(0) => repr_scan_in,
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scout(0) => repr_scan_out,
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---------------------------------------------
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din(0) => repr_in,
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---------------------------------------------
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dout(0) => repr_UNUSED
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---------------------------------------------
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);
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-- Unused logic
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spare_unused <= pc_fu_func_slp_sl_thold_3(1);
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end fuq_perv;
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