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1111 lines
58 KiB
VHDL
1111 lines
58 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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--//## some inputs and their latches can be droped (fr/fi always enabled together)
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--//## (ox/ux always enabled together)
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--//## spec always sets fr=fi=ox=ux=0
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--//##############################################################################
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-- cyc ex4 NORM : fpscr_rd
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-- cyc ex5 RND :
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-- cyc ex6 FPSCR : fpscr_wr
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--
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--
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-- FPSCR BIT DEFINITIONS
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-- ---------------- status 3:12,21:23 resetable
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-- [ 0] fx exception transition 0->1 (except mtfs,mtfsi)
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-- [ 1] fex "or" of enabled exceptions
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-- [ 2] vex "or" of invalid exceptions
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-- [ 3] ox
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-- [ 4] ux
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-- [ 5] zx
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-- [ 6] xx
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-- [ 7] vxsnan
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-- [ 8] vxisi (inf-sub-inf)
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-- [ 9] vxidi
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-- [10] vxzdz
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-- [11] vximz
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-- [12] vxvc
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-- [13] fr
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-- [14] fi
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-- [15] FPRF C
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-- [16] FPRF fpcc(lt)
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-- [17] FPRF fpcc(gt)
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-- [18] FPRF fpcc(eq)
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-- [19] FPRF fpcc(nan)
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-- [20] RESERVED
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-- [21] vx-soft
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-- [22] vx-sqrt
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-- [23] vx-vci
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-- -------------- control
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-- [24] ve
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-- [25] oe
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-- [26] ue
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-- [27] ze
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-- [28] xe
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-- [29] non-ieee
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-- [30:31] rnd_mode 00:nr 01:zr 02:pi 03:ni
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-----------------
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-- FPRF
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-- 10001 QNAN [0] qnan | den | (sign*zero)
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-- 01001 -INF [1] sign * !zero
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-- 01000 -norm [2] !sign * !zero * !qnan
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-- 11000 -den [3] zero
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-- 10010 -zero [4] inf | qnan
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-- 00010 +zero
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-- 10100 +den
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-- 00100 +norm
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-- 00101 +inf
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ENTITY fuq_scr IS
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generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other );
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PORT(
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vdd :inout power_logic;
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gnd :inout power_logic;
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clkoff_b :in std_ulogic; -- tiup
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act_dis :in std_ulogic; -- ??tidn??
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flush :in std_ulogic; -- ??tidn??
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delay_lclkr :in std_ulogic_vector(4 to 7); -- tidn,
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mpw1_b :in std_ulogic_vector(4 to 7); -- tidn,
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mpw2_b :in std_ulogic_vector(0 to 1); -- tidn,
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sg_1 :in std_ulogic;
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thold_1 :in std_ulogic;
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fpu_enable :in std_ulogic; --dc_act
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nclk :in clk_logic;
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f_scr_si :in std_ulogic ;-- perv
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f_scr_so :out std_ulogic ;-- perv
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ex2_act_b :in std_ulogic ;-- act writes
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f_cr2_ex3_thread_b :in std_ulogic_vector(0 to 3) ;-- thread write
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f_pic_ex5_scr_upd_move_b :in std_ulogic ;
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f_pic_ex5_scr_upd_pipe_b :in std_ulogic ;
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f_dcd_ex6_cancel :in std_ulogic ;
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f_pic_ex5_fprf_spec_b :in std_ulogic_vector(0 to 4) ;--FPRF for special cases
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f_pic_ex5_compare_b :in std_ulogic ;
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f_pic_ex5_fprf_pipe_v_b :in std_ulogic ;
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f_pic_ex5_fprf_hold_b :in std_ulogic ;--compare
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f_pic_ex5_fi_spec_b :in std_ulogic ;
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f_pic_ex5_fi_pipe_v_b :in std_ulogic ;
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f_pic_ex5_fr_spec_b :in std_ulogic ;
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f_pic_ex5_fr_pipe_v_b :in std_ulogic ;
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f_pic_ex5_ox_spec_b :in std_ulogic ;
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f_pic_ex5_ox_pipe_v_b :in std_ulogic ;
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f_pic_ex5_ux_spec_b :in std_ulogic ;
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f_pic_ex5_ux_pipe_v_b :in std_ulogic ;
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f_pic_ex5_flag_vxsnan_b :in std_ulogic ;--//# sig_nan
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f_pic_ex5_flag_vxisi_b :in std_ulogic ;--//# inf_sub_inf
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f_pic_ex5_flag_vxidi_b :in std_ulogic ;--//# inf_div_inf
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f_pic_ex5_flag_vxzdz_b :in std_ulogic ;--//# zer_div_zer
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f_pic_ex5_flag_vximz_b :in std_ulogic ;--//# inf_mul_zer
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f_pic_ex5_flag_vxvc_b :in std_ulogic ;--//# inval_cmp
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f_pic_ex5_flag_vxsqrt_b :in std_ulogic ;--//# inval_sqrt
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f_pic_ex5_flag_vxcvi_b :in std_ulogic ;--//# inval_convert
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f_pic_ex5_flag_zx_b :in std_ulogic ;--//# div_zer
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f_cr2_ex3_fpscr_bit_data_b :in std_ulogic_vector(0 to 3) ;
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f_cr2_ex3_fpscr_bit_mask_b :in std_ulogic_vector(0 to 3) ;
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f_cr2_ex3_fpscr_nib_mask_b :in std_ulogic_vector(0 to 8) ;
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f_cr2_ex3_mcrfs_b :in std_ulogic ;
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f_cr2_ex3_mtfsf_b :in std_ulogic ;
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f_cr2_ex3_mtfsfi_b :in std_ulogic ;
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f_cr2_ex3_mtfsbx_b :in std_ulogic ;
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f_nrm_ex5_fpscr_wr_dat_dfp :in std_ulogic_vector(0 to 3) ;
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f_scr_ex5_fpscr_rd_dat_dfp :out std_ulogic_vector(0 to 3) ;
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f_nrm_ex5_fpscr_wr_dat :in std_ulogic_vector(0 to 31) ;
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f_cr2_ex6_fpscr_rd_dat :in std_ulogic_vector(24 to 31) ;--//# for update
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f_cr2_ex5_fpscr_rd_dat :in std_ulogic_vector(24 to 31) ;--//# for mffs
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f_scr_ex5_fpscr_rd_dat :out std_ulogic_vector(0 to 31) ;--//# f_rnd
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f_rnd_ex6_flag_up :in std_ulogic ;
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f_rnd_ex6_flag_fi :in std_ulogic ;
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f_rnd_ex6_flag_ox :in std_ulogic ;
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f_rnd_ex6_flag_den :in std_ulogic ;
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f_rnd_ex6_flag_sgn :in std_ulogic ;
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f_rnd_ex6_flag_inf :in std_ulogic ;
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f_rnd_ex6_flag_zer :in std_ulogic ;
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f_rnd_ex6_flag_ux :in std_ulogic ;
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f_scr_ex7_cr_fld :out std_ulogic_vector(0 to 3) ;--//#iu
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f_scr_ex7_fx_thread0 :out std_ulogic_vector(0 to 3) ;--//#iu
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f_scr_ex7_fx_thread1 :out std_ulogic_vector(0 to 3) ;--//#iu
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f_scr_ex7_fx_thread2 :out std_ulogic_vector(0 to 3) ;--//#iu
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f_scr_ex7_fx_thread3 :out std_ulogic_vector(0 to 3) --//#iu
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); -- end ports
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end fuq_scr; -- ENTITY
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architecture fuq_scr of fuq_scr is
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constant tiup :std_ulogic := '1';
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constant tidn :std_ulogic := '0';
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signal sg_0 :std_ulogic ;
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signal thold_0_b , thold_0, forcee :std_ulogic ;
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signal ex3_act :std_ulogic ;
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signal ex2_act :std_ulogic ;
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signal ex4_act :std_ulogic ;
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signal ex5_act :std_ulogic ;
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signal ex6_act :std_ulogic ;
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signal ex6_th0_act :std_ulogic ;
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signal ex6_th1_act :std_ulogic ;
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signal ex6_th2_act :std_ulogic ;
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signal ex6_th3_act :std_ulogic ;
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signal ex6_th0_act_wocan :std_ulogic ;
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signal ex6_th1_act_wocan :std_ulogic ;
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signal ex6_th2_act_wocan :std_ulogic ;
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signal ex6_th3_act_wocan :std_ulogic ;
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signal act_spare_unused :std_ulogic_vector(0 to 3) ;
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-------------------
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signal act_so :std_ulogic_vector(0 to 13) ;--SCAN
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signal act_si :std_ulogic_vector(0 to 13) ;--SCAN
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signal ex4_ctl_so :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex4_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex5_ctl_so :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex5_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex6_ctl_so :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex6_ctl_si :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex6_flag_so :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex6_flag_si :std_ulogic_vector(0 to 24) ;--SCAN
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signal ex6_mvdat_so :std_ulogic_vector(0 to 27) ;--SCAN
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signal ex6_mvdat_si :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th0_so :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th0_si :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th1_so :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th1_si :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th2_so :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th2_si :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th3_so :std_ulogic_vector(0 to 27) ;--SCAN
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signal fpscr_th3_si :std_ulogic_vector(0 to 27) ;--SCAN
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signal ex7_crf_so :std_ulogic_vector(0 to 3) ;--SCAN
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signal ex7_crf_si :std_ulogic_vector(0 to 3) ;--SCAN
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-------------------
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signal ex6_mrg :std_ulogic_vector(0 to 23) ;
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signal ex6_mrg_dfp :std_ulogic_vector(0 to 3) ;
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signal ex6_fpscr_dfp_din :std_ulogic_vector(0 to 3) ;
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signal ex6_fpscr_din :std_ulogic_vector(0 to 23) ;
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signal ex6_cr_fld , ex6_cr_fld_x :std_ulogic_vector(0 to 3) ;
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signal ex6_fpscr_move :std_ulogic_vector(0 to 23) ;
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signal ex6_fpscr_pipe :std_ulogic_vector(0 to 23) ;
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signal ex6_fpscr_move_dfp :std_ulogic_vector(0 to 3) ;
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signal ex6_fpscr_pipe_dfp :std_ulogic_vector(0 to 3) ;
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signal fpscr_dfp_th0 :std_ulogic_vector(0 to 3) ;
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signal fpscr_dfp_th1 :std_ulogic_vector(0 to 3) ;
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signal fpscr_dfp_th2 :std_ulogic_vector(0 to 3) ;
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signal fpscr_dfp_th3 :std_ulogic_vector(0 to 3) ;
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signal fpscr_th0 :std_ulogic_vector(0 to 23) ;
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signal fpscr_th1 :std_ulogic_vector(0 to 23) ;
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signal fpscr_th2 :std_ulogic_vector(0 to 23) ;
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signal fpscr_th3 :std_ulogic_vector(0 to 23) ;
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signal fpscr_rd_dat :std_ulogic_vector(0 to 31) ;
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signal fpscr_rd_dat_dfp :std_ulogic_vector(0 to 3) ;
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signal ex7_cr_fld :std_ulogic_vector(0 to 3) ;
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signal ex6_fprf_pipe :std_ulogic_vector(0 to 4) ;
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signal ex4_thread :std_ulogic_vector(0 to 3) ;
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signal ex5_thread :std_ulogic_vector(0 to 3) ;
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signal ex6_thread :std_ulogic_vector(0 to 3) ;
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signal ex5_th0_act :std_ulogic ;
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signal ex5_th1_act :std_ulogic ;
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signal ex5_th2_act :std_ulogic ;
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signal ex5_th3_act :std_ulogic ;
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signal ex6_upd_move :std_ulogic ;
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signal ex6_upd_pipe :std_ulogic ;
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signal ex6_fprf_spec :std_ulogic_vector(0 to 4) ;
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signal ex6_compare :std_ulogic ;
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signal ex6_fprf_pipe_v :std_ulogic ;
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signal ex6_fprf_hold :std_ulogic ;
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signal ex6_fi_spec :std_ulogic ;
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signal ex6_fi_pipe_v :std_ulogic ;
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signal ex6_fr_spec :std_ulogic ;
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signal ex6_fr_pipe_v :std_ulogic ;
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signal ex6_ox_spec :std_ulogic ;
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signal ex6_ox_pipe_v :std_ulogic ;
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signal ex6_ux_spec :std_ulogic ;
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signal ex6_ux_pipe_v :std_ulogic ;
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signal ex6_mv_data :std_ulogic_vector(0 to 23) ;
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signal ex6_mv_data_dfp :std_ulogic_vector(0 to 3) ;
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signal ex6_mv_sel :std_ulogic_vector(0 to 23) ;
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signal ex6_mv_sel_dfp :std_ulogic_vector(0 to 3) ;
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signal ex6_flag_vxsnan :std_ulogic ;
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signal ex6_flag_vxisi :std_ulogic ;
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signal ex6_flag_vxidi :std_ulogic ;
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signal ex6_flag_vxzdz :std_ulogic ;
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signal ex6_flag_vximz :std_ulogic ;
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signal ex6_flag_vxvc :std_ulogic ;
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signal ex6_flag_vxsqrt :std_ulogic ;
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signal ex6_flag_vxcvi :std_ulogic ;
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signal ex6_flag_zx :std_ulogic ;
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signal ex6_fpscr_wr_dat :std_ulogic_vector(0 to 23) ;
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signal ex6_fpscr_wr_dat_dfp :std_ulogic_vector(0 to 3) ;
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signal ex6_new_excp :std_ulogic ;
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signal ex4_bit_data :std_ulogic_vector(0 to 3);
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signal ex4_bit_mask :std_ulogic_vector(0 to 3);
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signal ex4_nib_mask :std_ulogic_vector(0 to 8);
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signal ex4_mcrfs :std_ulogic;
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signal ex4_mtfsf :std_ulogic;
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signal ex4_mtfsfi :std_ulogic;
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signal ex4_mtfsbx :std_ulogic;
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signal ex5_bit_data :std_ulogic_vector(0 to 3);
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signal ex5_bit_mask :std_ulogic_vector(0 to 3);
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signal ex5_nib_mask :std_ulogic_vector(0 to 8);
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signal ex5_mcrfs :std_ulogic;
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signal ex5_mtfsf :std_ulogic;
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signal ex5_mtfsfi :std_ulogic;
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signal ex5_mtfsbx :std_ulogic;
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signal ex6_bit_data :std_ulogic_vector(0 to 3);
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signal ex6_bit_mask :std_ulogic_vector(0 to 3);
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signal ex6_nib_mask :std_ulogic_vector(0 to 8);
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signal ex6_mcrfs :std_ulogic;
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signal ex6_mtfsf :std_ulogic;
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signal ex6_mtfsfi :std_ulogic;
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signal ex6_mtfsbx :std_ulogic;
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signal unused_stuff :std_ulogic;
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signal ex5_scr_upd_move, ex5_scr_upd_pipe :std_ulogic ;
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signal ex3_thread :std_ulogic_vector(0 to 3);
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signal ex3_fpscr_bit_data :std_ulogic_vector(0 to 3);
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signal ex3_fpscr_bit_mask :std_ulogic_vector(0 to 3);
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signal ex3_fpscr_nib_mask :std_ulogic_vector(0 to 8);
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signal ex3_mcrfs :std_ulogic ;
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signal ex3_mtfsf :std_ulogic ;
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signal ex3_mtfsfi :std_ulogic ;
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signal ex3_mtfsbx :std_ulogic ;
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signal ex5_flag_vxsnan :std_ulogic;
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signal ex5_flag_vxisi :std_ulogic;
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signal ex5_flag_vxidi :std_ulogic;
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signal ex5_flag_vxzdz :std_ulogic;
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signal ex5_flag_vximz :std_ulogic;
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signal ex5_flag_vxvc :std_ulogic;
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signal ex5_flag_vxsqrt :std_ulogic;
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signal ex5_flag_vxcvi :std_ulogic;
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signal ex5_flag_zx :std_ulogic;
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signal ex5_fprf_spec :std_ulogic_vector(0 to 4);
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signal ex5_compare :std_ulogic;
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signal ex5_fprf_pipe_v :std_ulogic;
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signal ex5_fprf_hold :std_ulogic;
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signal ex5_fi_spec :std_ulogic;
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signal ex5_fi_pipe_v :std_ulogic;
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signal ex5_fr_spec :std_ulogic;
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signal ex5_fr_pipe_v :std_ulogic;
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signal ex5_ox_spec :std_ulogic;
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signal ex5_ox_pipe_v :std_ulogic;
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signal ex5_ux_spec :std_ulogic;
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signal ex5_ux_pipe_v :std_ulogic;
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signal ex6_upd_move_nmcrfs :std_ulogic;
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begin
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--//############################################
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--//# pervasive
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--//############################################
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thold_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => thold_1,
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q(0) => thold_0 );
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sg_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => sg_1 ,
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q(0) => sg_0 );
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lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
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clkoff_b => clkoff_b,
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thold => thold_0,
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sg => sg_0,
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act_dis => act_dis,
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forcee => forcee,
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thold_b => thold_0_b );
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--//############################################
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--//# ACT LATCHES
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--//############################################
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ex2_act <= not ex2_act_b ;
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ex5_scr_upd_move <= not f_pic_ex5_scr_upd_move_b ;
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ex5_scr_upd_pipe <= not f_pic_ex5_scr_upd_pipe_b ;
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act_lat: tri_rlmreg_p generic map (width=> 14, expand_type => expand_type) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(6) ,
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mpw1_b => mpw1_b(6) ,
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mpw2_b => mpw2_b(1) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => fpu_enable,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => act_so ,
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scin => act_si ,
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-------------------
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din(0) => act_spare_unused(0),
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din(1) => act_spare_unused(1),
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din(2) => ex2_act,
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din(3) => ex3_act,
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din(4) => ex4_act,
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din(5) => ex5_act,
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din(6) => ex5_th0_act ,
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din(7) => ex5_th1_act ,
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din(8) => ex5_th2_act ,
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din(9) => ex5_th3_act ,
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din(10) => ex5_scr_upd_move ,
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din(11) => ex5_scr_upd_pipe ,
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din(12) => act_spare_unused(2),
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din(13) => act_spare_unused(3),
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-------------------
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dout(0) => act_spare_unused(0),
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dout(1) => act_spare_unused(1),
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dout(2) => ex3_act,
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dout(3) => ex4_act,
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dout(4) => ex5_act,
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dout(5) => ex6_act,
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dout(6) => ex6_th0_act_wocan ,
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dout(7) => ex6_th1_act_wocan ,
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dout(8) => ex6_th2_act_wocan ,
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dout(9) => ex6_th3_act_wocan ,
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dout(10) => ex6_upd_move ,
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dout(11) => ex6_upd_pipe ,
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dout(12) => act_spare_unused(2) ,
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dout(13) => act_spare_unused(3) );
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ex5_th0_act <= ( ex5_thread(0) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ;
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ex5_th1_act <= ( ex5_thread(1) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ;
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ex5_th2_act <= ( ex5_thread(2) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ;
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ex5_th3_act <= ( ex5_thread(3) and ex5_act and ( ex5_scr_upd_move or ex5_scr_upd_pipe) ) ;
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ex6_th0_act <= ex6_th0_act_wocan and not f_dcd_ex6_cancel;
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ex6_th1_act <= ex6_th1_act_wocan and not f_dcd_ex6_cancel;
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ex6_th2_act <= ex6_th2_act_wocan and not f_dcd_ex6_cancel;
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ex6_th3_act <= ex6_th3_act_wocan and not f_dcd_ex6_cancel;
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--//##############################################
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--//# EX4 latches
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--//##############################################
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ex3_thread(0 to 3) <= not f_cr2_ex3_thread_b(0 to 3) ;
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ex3_fpscr_bit_data(0 to 3) <= not f_cr2_ex3_fpscr_bit_data_b(0 to 3) ;
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ex3_fpscr_bit_mask(0 to 3) <= not f_cr2_ex3_fpscr_bit_mask_b(0 to 3) ;
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ex3_fpscr_nib_mask(0 to 8) <= not f_cr2_ex3_fpscr_nib_mask_b(0 to 8) ;
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ex3_mcrfs <= not f_cr2_ex3_mcrfs_b ;
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ex3_mtfsf <= not f_cr2_ex3_mtfsf_b ;
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ex3_mtfsfi <= not f_cr2_ex3_mtfsfi_b ;
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ex3_mtfsbx <= not f_cr2_ex3_mtfsbx_b ;
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ex4_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(4) ,
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mpw1_b => mpw1_b(4) ,
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mpw2_b => mpw2_b(0) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => ex3_act ,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => ex4_ctl_so ,
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scin => ex4_ctl_si ,
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-------------------
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din(0 to 3) => ex3_thread(0 to 3) ,
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din(4 to 7) => ex3_fpscr_bit_data(0 to 3) ,
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din(8 to 11) => ex3_fpscr_bit_mask(0 to 3) ,
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din(12 to 20) => ex3_fpscr_nib_mask(0 to 8) ,
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din(21) => ex3_mcrfs ,
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din(22) => ex3_mtfsf ,
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din(23) => ex3_mtfsfi ,
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din(24) => ex3_mtfsbx ,
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-------------------
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dout(0 to 3) => ex4_thread(0 to 3) ,
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dout(4 to 7) => ex4_bit_data(0 to 3) ,
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dout(8 to 11) => ex4_bit_mask(0 to 3) ,
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dout(12 to 20) => ex4_nib_mask(0 to 8) ,
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dout(21) => ex4_mcrfs ,
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dout(22) => ex4_mtfsf ,
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dout(23) => ex4_mtfsfi ,
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dout(24) => ex4_mtfsbx );
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--//##############################################
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--//# EX5 latches
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--//##############################################
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ex5_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(5) ,
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mpw1_b => mpw1_b(5) ,
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mpw2_b => mpw2_b(1) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => ex4_act ,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => ex5_ctl_so ,
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scin => ex5_ctl_si ,
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-------------------
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din(0 to 3) => ex4_thread(0 to 3) ,
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din(4 to 7) => ex4_bit_data(0 to 3),
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din(8 to 11) => ex4_bit_mask(0 to 3),
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din(12 to 20) => ex4_nib_mask(0 to 8),
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din(21) => ex4_mcrfs ,
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din(22) => ex4_mtfsf ,
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din(23) => ex4_mtfsfi ,
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din(24) => ex4_mtfsbx ,
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-------------------
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dout(0 to 3) => ex5_thread(0 to 3) ,
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dout(4 to 7) => ex5_bit_data(0 to 3) ,
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dout(8 to 11) => ex5_bit_mask(0 to 3) ,
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dout(12 to 20) => ex5_nib_mask(0 to 8) ,
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dout(21) => ex5_mcrfs ,
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dout(22) => ex5_mtfsf ,
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dout(23) => ex5_mtfsfi ,
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dout(24) => ex5_mtfsbx );
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--//##############################################
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--//# EX6 latches
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--//##############################################
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ex6_ctl_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(6) ,
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mpw1_b => mpw1_b(6) ,
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mpw2_b => mpw2_b(1) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => ex5_act,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => ex6_ctl_so ,
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scin => ex6_ctl_si ,
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-------------------
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din(0 to 3) => ex5_thread(0 to 3),
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din(4 to 7) => ex5_bit_data(0 to 3),
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din(8 to 11) => ex5_bit_mask(0 to 3),
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din(12 to 20) => ex5_nib_mask(0 to 8),
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din(21) => ex5_mcrfs ,
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din(22) => ex5_mtfsf ,
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din(23) => ex5_mtfsfi ,
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din(24) => ex5_mtfsbx ,
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-------------------
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dout(0 to 3) => ex6_thread(0 to 3) ,
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dout(4 to 7) => ex6_bit_data(0 to 3) ,
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dout(8 to 11) => ex6_bit_mask(0 to 3) ,
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dout(12 to 20) => ex6_nib_mask(0 to 8) ,
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dout(21) => ex6_mcrfs ,
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dout(22) => ex6_mtfsf ,
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dout(23) => ex6_mtfsfi ,
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dout(24) => ex6_mtfsbx );
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ex5_flag_vxsnan <= not f_pic_ex5_flag_vxsnan_b ;
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ex5_flag_vxisi <= not f_pic_ex5_flag_vxisi_b ;
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ex5_flag_vxidi <= not f_pic_ex5_flag_vxidi_b ;
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ex5_flag_vxzdz <= not f_pic_ex5_flag_vxzdz_b ;
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ex5_flag_vximz <= not f_pic_ex5_flag_vximz_b ;
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ex5_flag_vxvc <= not f_pic_ex5_flag_vxvc_b ;
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ex5_flag_vxsqrt <= not f_pic_ex5_flag_vxsqrt_b ;
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ex5_flag_vxcvi <= not f_pic_ex5_flag_vxcvi_b ;
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ex5_flag_zx <= not f_pic_ex5_flag_zx_b ;
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ex5_fprf_spec(0 to 4) <= not f_pic_ex5_fprf_spec_b(0 to 4) ;
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ex5_compare <= not f_pic_ex5_compare_b ;
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ex5_fprf_pipe_v <= not f_pic_ex5_fprf_pipe_v_b ;
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ex5_fprf_hold <= not f_pic_ex5_fprf_hold_b ;
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ex5_fi_spec <= not f_pic_ex5_fi_spec_b ;
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ex5_fi_pipe_v <= not f_pic_ex5_fi_pipe_v_b ;
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ex5_fr_spec <= not f_pic_ex5_fr_spec_b ;
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ex5_fr_pipe_v <= not f_pic_ex5_fr_pipe_v_b ;
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ex5_ox_spec <= not f_pic_ex5_ox_spec_b ;
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ex5_ox_pipe_v <= not f_pic_ex5_ox_pipe_v_b ;
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ex5_ux_spec <= not f_pic_ex5_ux_spec_b ;
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ex5_ux_pipe_v <= not f_pic_ex5_ux_pipe_v_b ;
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ex6_flag_lat: tri_rlmreg_p generic map (width=> 25, expand_type => expand_type) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(6) ,
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mpw1_b => mpw1_b(6) ,
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mpw2_b => mpw2_b(1) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => ex5_act,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => ex6_flag_so ,
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scin => ex6_flag_si ,
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-------------------
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din(0) => ex5_flag_vxsnan ,--//# sig_nan
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din(1) => ex5_flag_vxisi ,--//# inf_sub_inf
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din(2) => ex5_flag_vxidi ,--//# inf_div_inf
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din(3) => ex5_flag_vxzdz ,--//# zer_div_zer
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din(4) => ex5_flag_vximz ,--//# inf_mul_zer
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din(5) => ex5_flag_vxvc ,--//# inval_cmp
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din(6) => ex5_flag_vxsqrt ,--//# inval_sqrt
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din(7) => ex5_flag_vxcvi ,--//# inval_convert
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din(8) => ex5_flag_zx ,--//# div_zer
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din(9 to 13) => ex5_fprf_spec(0 to 4) ,--FPRF/'0'FPCC for special cases
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din(14) => ex5_compare ,
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din(15) => ex5_fprf_pipe_v ,--fprf update exluding compare
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din(16) => ex5_fprf_hold ,--fprf update including compare
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din(17) => ex5_fi_spec ,
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din(18) => ex5_fi_pipe_v ,
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din(19) => ex5_fr_spec ,
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din(20) => ex5_fr_pipe_v ,
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din(21) => ex5_ox_spec ,
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din(22) => ex5_ox_pipe_v ,
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din(23) => ex5_ux_spec ,
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din(24) => ex5_ux_pipe_v ,
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-------------------
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dout(0) => ex6_flag_vxsnan ,--LAT--
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dout(1) => ex6_flag_vxisi ,--LAT--
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dout(2) => ex6_flag_vxidi ,--LAT--
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dout(3) => ex6_flag_vxzdz ,--LAT--
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dout(4) => ex6_flag_vximz ,--LAT--
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dout(5) => ex6_flag_vxvc ,--LAT--
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dout(6) => ex6_flag_vxsqrt ,--LAT--
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dout(7) => ex6_flag_vxcvi ,--LAT--
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dout(8) => ex6_flag_zx ,--LAT--
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dout(9 to 13) => ex6_fprf_spec (0 to 4) ,--LAT--
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dout(14) => ex6_compare ,--LAT--
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dout(15) => ex6_fprf_pipe_v ,--LAT--
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dout(16) => ex6_fprf_hold ,--LAT--
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dout(17) => ex6_fi_spec ,--LAT--
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dout(18) => ex6_fi_pipe_v ,--LAT--
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dout(19) => ex6_fr_spec ,--LAT--
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dout(20) => ex6_fr_pipe_v ,--LAT--
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dout(21) => ex6_ox_spec ,--LAT--
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dout(22) => ex6_ox_pipe_v ,--LAT--
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dout(23) => ex6_ux_spec ,--LAT--
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dout(24) => ex6_ux_pipe_v );--LAT--
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ex6_mvdat_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(6) ,
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mpw1_b => mpw1_b(6) ,
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mpw2_b => mpw2_b(1) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => ex5_act,
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thold_b => thold_0_b,
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sg => sg_0,
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scout => ex6_mvdat_so ,
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scin => ex6_mvdat_si ,
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-------------------
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din(0 to 3) => f_nrm_ex5_fpscr_wr_dat_dfp(0 to 3) ,
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din(4 to 27) => f_nrm_ex5_fpscr_wr_dat(0 to 23) ,
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dout(0 to 3) => ex6_fpscr_wr_dat_dfp(0 to 3) ,--LAT--
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dout(4 to 27) => ex6_fpscr_wr_dat(0 to 23) );--LAT--
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--//##############################################
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--//# EX6 logic
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--//##############################################
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--//#-----------------------------------------
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--//# select field for mcrfs
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--//#-----------------------------------------
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ex6_cr_fld_x(0 to 3) <=
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( ex6_mrg( 0 to 3) and (0 to 3=> ex6_nib_mask(0) ) ) or
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( ex6_mrg( 4 to 7) and (0 to 3=> ex6_nib_mask(1) ) ) or
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( ex6_mrg( 8 to 11) and (0 to 3=> ex6_nib_mask(2) ) ) or
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( ex6_mrg(12 to 15) and (0 to 3=> ex6_nib_mask(3) ) ) or
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( ex6_mrg(16 to 19) and (0 to 3=> ex6_nib_mask(4) ) ) or
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( (tidn & ex6_mrg(21 to 23)) and (0 to 3=> ex6_nib_mask(5) ) ) or --[20] is a reserved bit
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( f_cr2_ex6_fpscr_rd_dat(24 to 27) and (0 to 3=> ex6_nib_mask(6) ) ) or
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( f_cr2_ex6_fpscr_rd_dat(28 to 31) and (0 to 3=> ex6_nib_mask(7) ) );
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ex6_upd_move_nmcrfs <= ex6_upd_move and not ex6_mcrfs ;
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ex6_cr_fld(0 to 3) <=
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( ex6_mrg(0 to 3) and (0 to 3 => not ex6_upd_move and not ex6_upd_pipe) ) or -- fmr
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( ex6_cr_fld_x(0 to 3) and (0 to 3 => ex6_mcrfs ) ) or -- the old value
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( ex6_fpscr_din(0 to 3) and (0 to 3 => ex6_upd_pipe ) ) or -- what the math update will be
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( ex6_fpscr_din(0 to 3) and (0 to 3 => ex6_upd_move_nmcrfs ) ) ; -- what the math update will be
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--//#-----------------------------------------------------------------------
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--//# move to logic mtfsf mtfsfi mcrf mtfsb0 mtfsb1
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--//#-----------------------------------------------------------------------
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-- if mcrfs : if nib_mask selects -> reset if (0,3:12,21:23) (bit mask=1111)
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-- if mtfsfi : if nib_mask selects -> load with bit data (bit mask=1111)
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-- if mtfsf : if nib_mask selects -> load with wr_data (bit mask=1111)
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-- if mtfsb0 : if nib_mask selects -> load with bit data (if bit mask)
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-- if mtfsb1 : if nib_mask selects -> load with bit_data (if bit mask)
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ex6_mv_data_dfp(0 to 3) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat_dfp(0 to 3) and (0 to 3 => ex6_mtfsf) );
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ex6_mv_data( 0 to 3) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 0 to 3) and (0 to 3 => ex6_mtfsf) );
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ex6_mv_data( 4 to 7) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 4 to 7) and (0 to 3 => ex6_mtfsf) );
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ex6_mv_data( 8 to 11) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat( 8 to 11) and (0 to 3 => ex6_mtfsf) );
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ex6_mv_data(12 to 15) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(12 to 15) and (0 to 3 => ex6_mtfsf) );
|
|
ex6_mv_data(16 to 19) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(16 to 19) and (0 to 3 => ex6_mtfsf) );
|
|
ex6_mv_data(20 to 23) <= ( ex6_bit_data(0 to 3) and (0 to 3 => not ex6_mtfsf) ) or (ex6_fpscr_wr_dat(20 to 23) and (0 to 3 => ex6_mtfsf) );
|
|
|
|
|
|
ex6_mv_sel_dfp(0) <= ex6_bit_mask(0) and ex6_nib_mask(8) ;
|
|
ex6_mv_sel_dfp(1) <= ex6_bit_mask(1) and ex6_nib_mask(8) ;
|
|
ex6_mv_sel_dfp(2) <= ex6_bit_mask(2) and ex6_nib_mask(8) ;
|
|
ex6_mv_sel_dfp(3) <= ex6_bit_mask(3) and ex6_nib_mask(8) ;
|
|
|
|
ex6_mv_sel( 0) <= ex6_bit_mask(0) and ex6_nib_mask(0) ; -- fx
|
|
ex6_mv_sel( 1) <= tidn; --UNUSED -- fex
|
|
ex6_mv_sel( 2) <= tidn; --UNUSED -- vx
|
|
ex6_mv_sel( 3) <= ex6_bit_mask(3) and ex6_nib_mask(0) ; -- ox
|
|
ex6_mv_sel( 4) <= ex6_bit_mask(0) and ex6_nib_mask(1) ; -- ux
|
|
ex6_mv_sel( 5) <= ex6_bit_mask(1) and ex6_nib_mask(1) ; -- zx
|
|
ex6_mv_sel( 6) <= ex6_bit_mask(2) and ex6_nib_mask(1) ; -- xx
|
|
ex6_mv_sel( 7) <= ex6_bit_mask(3) and ex6_nib_mask(1) ; -- vxsnan
|
|
ex6_mv_sel( 8) <= ex6_bit_mask(0) and ex6_nib_mask(2) ; -- vxisi
|
|
ex6_mv_sel( 9) <= ex6_bit_mask(1) and ex6_nib_mask(2) ; -- vxidi
|
|
ex6_mv_sel(10) <= ex6_bit_mask(2) and ex6_nib_mask(2) ; -- vxzdz
|
|
ex6_mv_sel(11) <= ex6_bit_mask(3) and ex6_nib_mask(2) ; -- vximz
|
|
ex6_mv_sel(12) <= ex6_bit_mask(0) and ex6_nib_mask(3) ; -- vxvc
|
|
ex6_mv_sel(13) <= ex6_bit_mask(1) and ex6_nib_mask(3) and not ex6_mcrfs; -- fr
|
|
ex6_mv_sel(14) <= ex6_bit_mask(2) and ex6_nib_mask(3) and not ex6_mcrfs; -- fi
|
|
ex6_mv_sel(15) <= ex6_bit_mask(3) and ex6_nib_mask(3) and not ex6_mcrfs; -- FPRF C
|
|
ex6_mv_sel(16) <= ex6_bit_mask(0) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(lt)
|
|
ex6_mv_sel(17) <= ex6_bit_mask(1) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(gt)
|
|
ex6_mv_sel(18) <= ex6_bit_mask(2) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(eq)
|
|
ex6_mv_sel(19) <= ex6_bit_mask(3) and ex6_nib_mask(4) and not ex6_mcrfs; -- FPRF fpcc(nan)
|
|
ex6_mv_sel(20) <= ex6_bit_mask(0) and ex6_nib_mask(5) and not ex6_mcrfs; -- RESERVED
|
|
ex6_mv_sel(21) <= ex6_bit_mask(1) and ex6_nib_mask(5) ; -- vx-soft
|
|
ex6_mv_sel(22) <= ex6_bit_mask(2) and ex6_nib_mask(5) ; -- vx-sqrt
|
|
ex6_mv_sel(23) <= ex6_bit_mask(3) and ex6_nib_mask(5) ; -- vx-vci
|
|
|
|
ex6_fpscr_move( 0) <= (ex6_mrg( 0) and not ex6_mv_sel( 0)) or (ex6_mv_data(0) and ex6_mv_sel( 0) );
|
|
ex6_fpscr_move( 1) <= tidn; --//unused (from other bits after move/pipe selection)
|
|
ex6_fpscr_move( 2) <= tidn; --//unused (from other bits after move/pipe selection)
|
|
ex6_fpscr_move( 3 to 23) <=
|
|
( ex6_mrg(3 to 23) and not ex6_mv_sel(3 to 23) ) or
|
|
( ex6_mv_data(3 to 23) and ex6_mv_sel(3 to 23) ) ;
|
|
|
|
ex6_fpscr_move_dfp(0 to 3) <=
|
|
( ex6_mrg_dfp(0 to 3) and not ex6_mv_sel_dfp(0 to 3) ) or
|
|
( ex6_mv_data_dfp(0 to 3) and ex6_mv_sel_dfp(0 to 3) ) ;
|
|
|
|
--//#------------------------------------------------------------------------
|
|
--//# decode fprf field for pipe settings
|
|
--//#------------------------------------------------------------------------
|
|
-- FPRF
|
|
-- 10001 QNAN [0] qnan | den | (sign*zero)
|
|
-- 01001 -INF [1] sign * !zero
|
|
-- 01000 -norm [2] !sign * !zero * !qnan
|
|
-- 11000 -den [3] zero
|
|
-- 10010 -zero [4] inf | qnan
|
|
-- 00010 +zero
|
|
-- 10100 +den
|
|
-- 00100 +norm
|
|
-- 00101 +inf
|
|
|
|
ex6_fprf_pipe(0) <= ( f_rnd_ex6_flag_sgn and f_rnd_ex6_flag_zer) or
|
|
( f_rnd_ex6_flag_den and not f_rnd_ex6_flag_zer) ;
|
|
|
|
ex6_fprf_pipe(1) <= ( f_rnd_ex6_flag_sgn and not f_rnd_ex6_flag_zer);
|
|
ex6_fprf_pipe(2) <= (not f_rnd_ex6_flag_sgn and not f_rnd_ex6_flag_zer);
|
|
ex6_fprf_pipe(3) <= f_rnd_ex6_flag_zer;
|
|
ex6_fprf_pipe(4) <= f_rnd_ex6_flag_inf ;
|
|
|
|
--//#------------------------------------------------------------------------
|
|
--//# functional updates (excp enable cases, special setting vs pipe setting)
|
|
--//#------------------------------------------------------------------------
|
|
|
|
ex6_fpscr_pipe( 0) <= ex6_mrg( 0) ; -- <sticky aspect> check 0->1 excp after selection for move/pipe
|
|
ex6_fpscr_pipe( 1) <= tidn ; --// unused (from other bits after move/pipe selection)
|
|
ex6_fpscr_pipe( 2) <= tidn ; --// unused (from other bits after move/pipe selection)
|
|
ex6_fpscr_pipe( 3) <= ex6_mrg( 3) or --ox STICKY
|
|
ex6_ox_spec or
|
|
(ex6_ox_pipe_v and f_rnd_ex6_flag_ox );
|
|
ex6_fpscr_pipe( 4) <= ex6_mrg( 4) or --ux STICKY
|
|
ex6_ux_spec or
|
|
(ex6_ux_pipe_v and f_rnd_ex6_flag_ux );
|
|
ex6_fpscr_pipe( 5) <= ex6_mrg( 5) or ex6_flag_zx ; --sticky
|
|
|
|
ex6_fpscr_pipe( 6) <= (ex6_mrg( 6) ) or -- ex6_fpscr_pipe(14); --sticky version of fi
|
|
(ex6_fi_spec ) or
|
|
(ex6_fi_pipe_v and f_rnd_ex6_flag_fi );
|
|
|
|
ex6_fpscr_pipe( 7) <= ex6_mrg( 7) or ex6_flag_vxsnan ; --sticky
|
|
ex6_fpscr_pipe( 8) <= ex6_mrg( 8) or ex6_flag_vxisi ; --sticky
|
|
ex6_fpscr_pipe( 9) <= ex6_mrg( 9) or ex6_flag_vxidi ; --sticky
|
|
ex6_fpscr_pipe(10) <= ex6_mrg(10) or ex6_flag_vxzdz ; --sticky
|
|
ex6_fpscr_pipe(11) <= ex6_mrg(11) or ex6_flag_vximz ; --sticky
|
|
ex6_fpscr_pipe(12) <= ex6_mrg(12) or ex6_flag_vxvc ; --sticky
|
|
|
|
|
|
ex6_fpscr_pipe(13) <= --fr NOT sticky
|
|
(ex6_mrg(13) and ex6_compare ) or
|
|
(ex6_fr_spec ) or
|
|
(ex6_fr_pipe_v and f_rnd_ex6_flag_up );
|
|
ex6_fpscr_pipe(14) <= --fi NOT sticky
|
|
(ex6_mrg(14) and ex6_compare ) or
|
|
(ex6_fi_spec ) or
|
|
(ex6_fi_pipe_v and f_rnd_ex6_flag_fi );
|
|
|
|
|
|
|
|
ex6_fpscr_pipe(15) <= --FPRF C NOT sticky
|
|
(ex6_mrg(15) and ex6_fprf_hold ) or
|
|
(ex6_mrg(15) and ex6_compare ) or
|
|
(ex6_fprf_spec(0) ) or
|
|
(ex6_fprf_pipe_v and ex6_fprf_pipe(0) ) ;
|
|
|
|
|
|
ex6_fpscr_pipe(16) <= --FPRF fpdd(lt)
|
|
(ex6_mrg(16) and ex6_fprf_hold ) or
|
|
(ex6_fprf_spec(1) ) or
|
|
(ex6_fprf_pipe_v and ex6_fprf_pipe(1) ) ;
|
|
ex6_fpscr_pipe(17) <= --FPRF fpcc(gt)
|
|
(ex6_mrg(17) and ex6_fprf_hold ) or
|
|
(ex6_fprf_spec(2) ) or
|
|
(ex6_fprf_pipe_v and ex6_fprf_pipe(2) ) ;
|
|
ex6_fpscr_pipe(18) <= --FPRF fpcc(eq)
|
|
(ex6_mrg(18) and ex6_fprf_hold ) or
|
|
(ex6_fprf_spec(3) ) or
|
|
(ex6_fprf_pipe_v and ex6_fprf_pipe(3) ) ;
|
|
ex6_fpscr_pipe(19) <= --FPRF fpcc(nan)
|
|
(ex6_mrg(19) and ex6_fprf_hold ) or
|
|
(ex6_fprf_spec(4) ) or
|
|
(ex6_fprf_pipe_v and ex6_fprf_pipe(4) ) ;
|
|
|
|
ex6_fpscr_pipe(20) <= tidn ; -- reseved bit <UNUSED>
|
|
ex6_fpscr_pipe(21) <= ex6_mrg(21) ; -- VXSOFT
|
|
ex6_fpscr_pipe(22) <= ex6_mrg(22) or ex6_flag_vxsqrt ;--sticky
|
|
ex6_fpscr_pipe(23) <= ex6_mrg(23) or ex6_flag_vxcvi ;--sticky
|
|
|
|
ex6_fpscr_pipe_dfp(0 to 3) <= ex6_mrg_dfp(0 to 3);
|
|
|
|
|
|
--//#------------------------------------------------------------------------
|
|
--//# creating the funny or bits afer the selection
|
|
--//#------------------------------------------------------------------------
|
|
|
|
|
|
ex6_fpscr_dfp_din(0) <= (ex6_fpscr_move_dfp(0) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(0) and ex6_upd_pipe) ;
|
|
ex6_fpscr_dfp_din(1) <= (ex6_fpscr_move_dfp(1) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(1) and ex6_upd_pipe) ;
|
|
ex6_fpscr_dfp_din(2) <= (ex6_fpscr_move_dfp(2) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(2) and ex6_upd_pipe) ;
|
|
ex6_fpscr_dfp_din(3) <= (ex6_fpscr_move_dfp(3) and ex6_upd_move) or (ex6_fpscr_pipe_dfp(3) and ex6_upd_pipe) ;
|
|
|
|
|
|
ex6_fpscr_din(23) <= (ex6_fpscr_move(23) and ex6_upd_move) or (ex6_fpscr_pipe(23) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(22) <= (ex6_fpscr_move(22) and ex6_upd_move) or (ex6_fpscr_pipe(22) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(21) <= (ex6_fpscr_move(21) and ex6_upd_move) or (ex6_fpscr_pipe(21) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(20) <= tidn; -- reserved
|
|
ex6_fpscr_din(19) <= (ex6_fpscr_move(19) and ex6_upd_move) or (ex6_fpscr_pipe(19) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(18) <= (ex6_fpscr_move(18) and ex6_upd_move) or (ex6_fpscr_pipe(18) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(17) <= (ex6_fpscr_move(17) and ex6_upd_move) or (ex6_fpscr_pipe(17) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(16) <= (ex6_fpscr_move(16) and ex6_upd_move) or (ex6_fpscr_pipe(16) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(15) <= (ex6_fpscr_move(15) and ex6_upd_move) or (ex6_fpscr_pipe(15) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(14) <= (ex6_fpscr_move(14) and ex6_upd_move) or (ex6_fpscr_pipe(14) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(13) <= (ex6_fpscr_move(13) and ex6_upd_move) or (ex6_fpscr_pipe(13) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(12) <= (ex6_fpscr_move(12) and ex6_upd_move) or (ex6_fpscr_pipe(12) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(11) <= (ex6_fpscr_move(11) and ex6_upd_move) or (ex6_fpscr_pipe(11) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din(10) <= (ex6_fpscr_move(10) and ex6_upd_move) or (ex6_fpscr_pipe(10) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din( 9) <= (ex6_fpscr_move( 9) and ex6_upd_move) or (ex6_fpscr_pipe( 9) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din( 8) <= (ex6_fpscr_move( 8) and ex6_upd_move) or (ex6_fpscr_pipe( 8) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din( 7) <= (ex6_fpscr_move( 7) and ex6_upd_move) or (ex6_fpscr_pipe( 7) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din( 6) <= (ex6_fpscr_move( 6) and ex6_upd_move) or (ex6_fpscr_pipe( 6) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din( 5) <= (ex6_fpscr_move( 5) and ex6_upd_move) or (ex6_fpscr_pipe( 5) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din( 4) <= (ex6_fpscr_move( 4) and ex6_upd_move) or (ex6_fpscr_pipe( 4) and ex6_upd_pipe) ;
|
|
ex6_fpscr_din( 3) <= (ex6_fpscr_move( 3) and ex6_upd_move) or (ex6_fpscr_pipe( 3) and ex6_upd_pipe) ;
|
|
|
|
ex6_fpscr_din(2) <= -- or all invalid operation exceptions
|
|
ex6_fpscr_din(7) or -- vxsnan
|
|
ex6_fpscr_din(8) or -- vxisi
|
|
ex6_fpscr_din(9) or -- vxidi
|
|
ex6_fpscr_din(10) or -- vxzdz
|
|
ex6_fpscr_din(11) or -- vximx
|
|
ex6_fpscr_din(12) or -- vxvc
|
|
ex6_fpscr_din(21) or -- vxzdz
|
|
ex6_fpscr_din(22) or -- vximx
|
|
ex6_fpscr_din(23) ; -- vxvc
|
|
|
|
ex6_fpscr_din(1) <= -- masked or of all exception bits
|
|
( ex6_fpscr_din(2) and f_cr2_ex6_fpscr_rd_dat(24) ) or -- vx* / ve
|
|
( ex6_fpscr_din(3) and f_cr2_ex6_fpscr_rd_dat(25) ) or -- ox / oe
|
|
( ex6_fpscr_din(4) and f_cr2_ex6_fpscr_rd_dat(26) ) or -- ux / ue
|
|
( ex6_fpscr_din(5) and f_cr2_ex6_fpscr_rd_dat(27) ) or -- zx / ze
|
|
( ex6_fpscr_din(6) and f_cr2_ex6_fpscr_rd_dat(28) ) ; -- xx / xe
|
|
|
|
ex6_fpscr_din( 0) <=
|
|
(ex6_fpscr_move( 0) and ex6_upd_move) or
|
|
(ex6_fpscr_pipe( 0) and ex6_upd_pipe) or
|
|
(ex6_new_excp and not ex6_mtfsf and not ex6_mtfsfi );
|
|
|
|
ex6_new_excp <= -- only check the exception bits
|
|
(not ex6_mrg( 3) and ex6_fpscr_din( 3) ) or -- ox
|
|
(not ex6_mrg( 4) and ex6_fpscr_din( 4) ) or -- ux
|
|
(not ex6_mrg( 5) and ex6_fpscr_din( 5) ) or -- zx
|
|
(not ex6_mrg( 6) and ex6_fpscr_din( 6) ) or -- xx
|
|
(not ex6_mrg( 7) and ex6_fpscr_din( 7) ) or -- vxsnan
|
|
(not ex6_mrg( 8) and ex6_fpscr_din( 8) ) or -- vxisi
|
|
(not ex6_mrg( 9) and ex6_fpscr_din( 9) ) or -- vxidi
|
|
(not ex6_mrg(10) and ex6_fpscr_din(10) ) or -- vxzdz
|
|
(not ex6_mrg(11) and ex6_fpscr_din(11) ) or -- vximx
|
|
(not ex6_mrg(12) and ex6_fpscr_din(12) ) or -- vxvc
|
|
(not ex6_mrg(21) and ex6_fpscr_din(21) ) or -- vxzdz
|
|
(not ex6_mrg(22) and ex6_fpscr_din(22) ) or -- vximx
|
|
(not ex6_mrg(23) and ex6_fpscr_din(23) ) ; -- vxvc
|
|
|
|
|
|
|
|
--//##############################################
|
|
--//# EX7 latches
|
|
--//##############################################
|
|
|
|
|
|
fpscr_th0_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map (
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr(7) ,
|
|
mpw1_b => mpw1_b(7) ,
|
|
mpw2_b => mpw2_b(1) ,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
thold_b => thold_0_b,
|
|
sg => sg_0,
|
|
act => ex6_th0_act,
|
|
scout => fpscr_th0_so ,
|
|
scin => fpscr_th0_si ,
|
|
-------------------
|
|
din(0 to 3) => ex6_fpscr_dfp_din(0 to 3),
|
|
din(4 to 27) => ex6_fpscr_din(0 to 23),
|
|
dout(0 to 3) => fpscr_dfp_th0(0 to 3) ,--LAT--
|
|
dout(4 to 27) => fpscr_th0(0 to 23) );--LAT--
|
|
|
|
fpscr_th1_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map (
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr(7) ,
|
|
mpw1_b => mpw1_b(7) ,
|
|
mpw2_b => mpw2_b(1) ,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
thold_b => thold_0_b,
|
|
sg => sg_0,
|
|
act => ex6_th1_act,
|
|
scout => fpscr_th1_so ,
|
|
scin => fpscr_th1_si ,
|
|
-------------------
|
|
din(0 to 3) => ex6_fpscr_dfp_din(0 to 3),
|
|
din(4 to 27) => ex6_fpscr_din(0 to 23),
|
|
dout(0 to 3) => fpscr_dfp_th1(0 to 3) ,--LAT--
|
|
dout(4 to 27) => fpscr_th1(0 to 23) );--LAT--
|
|
|
|
fpscr_th2_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map (
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr(7) ,
|
|
mpw1_b => mpw1_b(7) ,
|
|
mpw2_b => mpw2_b(1) ,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
thold_b => thold_0_b,
|
|
sg => sg_0,
|
|
act => ex6_th2_act,
|
|
scout => fpscr_th2_so ,
|
|
scin => fpscr_th2_si ,
|
|
-------------------
|
|
din(0 to 3) => ex6_fpscr_dfp_din(0 to 3),
|
|
din(4 to 27) => ex6_fpscr_din(0 to 23),
|
|
dout(0 to 3) => fpscr_dfp_th2(0 to 3) ,--LAT--
|
|
dout(4 to 27) => fpscr_th2(0 to 23) );--LAT--
|
|
|
|
fpscr_th3_lat: tri_rlmreg_p generic map (width=> 28, expand_type => expand_type) port map (
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr(7) ,
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mpw1_b => mpw1_b(7) ,
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mpw2_b => mpw2_b(1) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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thold_b => thold_0_b,
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sg => sg_0,
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act => ex6_th3_act,
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scout => fpscr_th3_so ,
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scin => fpscr_th3_si ,
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-------------------
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din(0 to 3) => ex6_fpscr_dfp_din(0 to 3),
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din(4 to 27) => ex6_fpscr_din(0 to 23),
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dout(0 to 3) => fpscr_dfp_th3(0 to 3) ,--LAT--
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dout(4 to 27) => fpscr_th3(0 to 23) );--LAT--
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ex7_crf_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(7) ,
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mpw1_b => mpw1_b(7) ,
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mpw2_b => mpw2_b(1) ,
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vd => vdd,
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|
gd => gnd,
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|
nclk => nclk,
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|
act => ex6_act,
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|
thold_b => thold_0_b,
|
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sg => sg_0,
|
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scout => ex7_crf_so ,
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|
scin => ex7_crf_si ,
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-------------------
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|
din => ex6_cr_fld(0 to 3),
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dout => ex7_cr_fld(0 to 3) );--LAT--
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f_scr_ex7_cr_fld(0 to 3) <= ex7_cr_fld(0 to 3) ;--output--//#iu
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f_scr_ex7_fx_thread0(0 to 3) <= fpscr_th0(0 to 3) ;--output--//#iu
|
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f_scr_ex7_fx_thread1(0 to 3) <= fpscr_th1(0 to 3) ;--output--//#iu
|
|
f_scr_ex7_fx_thread2(0 to 3) <= fpscr_th2(0 to 3) ;--output--//#iu
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f_scr_ex7_fx_thread3(0 to 3) <= fpscr_th3(0 to 3) ;--output--//#iu
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|
|
|
--//##############################################
|
|
--//# read fpscr (mixed cycles)
|
|
--//##############################################
|
|
|
|
fpscr_rd_dat_dfp(0 to 3) <= -- write data to bit 20 is "0"
|
|
( fpscr_dfp_th0(0 to 3) and (0 to 3 => ex5_thread(0) ) ) or
|
|
( fpscr_dfp_th1(0 to 3) and (0 to 3 => ex5_thread(1) ) ) or
|
|
( fpscr_dfp_th2(0 to 3) and (0 to 3 => ex5_thread(2) ) ) or
|
|
( fpscr_dfp_th3(0 to 3) and (0 to 3 => ex5_thread(3) ) ) ;
|
|
|
|
fpscr_rd_dat(0 to 23) <= -- write data to bit 20 is "0"
|
|
( fpscr_th0(0 to 23) and (0 to 23 => ex5_thread(0) ) ) or
|
|
( fpscr_th1(0 to 23) and (0 to 23 => ex5_thread(1) ) ) or
|
|
( fpscr_th2(0 to 23) and (0 to 23 => ex5_thread(2) ) ) or
|
|
( fpscr_th3(0 to 23) and (0 to 23 => ex5_thread(3) ) ) ;
|
|
|
|
ex6_mrg_dfp(0 to 3) <= -- write data to bit 20 is "0"
|
|
( fpscr_dfp_th0(0 to 3) and (0 to 3 => ex6_thread(0) ) ) or
|
|
( fpscr_dfp_th1(0 to 3) and (0 to 3 => ex6_thread(1) ) ) or
|
|
( fpscr_dfp_th2(0 to 3) and (0 to 3 => ex6_thread(2) ) ) or
|
|
( fpscr_dfp_th3(0 to 3) and (0 to 3 => ex6_thread(3) ) ) ;
|
|
|
|
ex6_mrg(0 to 23) <= -- write data to bit 20 is "0"
|
|
( fpscr_th0(0 to 23) and (0 to 23 => ex6_thread(0) ) ) or
|
|
( fpscr_th1(0 to 23) and (0 to 23 => ex6_thread(1) ) ) or
|
|
( fpscr_th2(0 to 23) and (0 to 23 => ex6_thread(2) ) ) or
|
|
( fpscr_th3(0 to 23) and (0 to 23 => ex6_thread(3) ) ) ;
|
|
|
|
|
|
|
|
fpscr_rd_dat (24 to 31) <= f_cr2_ex5_fpscr_rd_dat(24 to 31) ;
|
|
f_scr_ex5_fpscr_rd_dat(0 to 31) <= fpscr_rd_dat(0 to 31) ;--output--//#f_rnd
|
|
f_scr_ex5_fpscr_rd_dat_dfp(0 to 3) <= fpscr_rd_dat_dfp(0 to 3) ;
|
|
|
|
--//############################################
|
|
--//# scan
|
|
--//############################################
|
|
|
|
|
|
ex4_ctl_si (0 to 24) <= ex4_ctl_so (1 to 24) & f_scr_si;
|
|
ex5_ctl_si (0 to 24) <= ex5_ctl_so (1 to 24) & ex4_ctl_so (0);
|
|
ex6_ctl_si (0 to 24) <= ex6_ctl_so (1 to 24) & ex5_ctl_so (0);
|
|
ex6_flag_si (0 to 24) <= ex6_flag_so (1 to 24) & ex6_ctl_so (0);
|
|
ex6_mvdat_si (0 to 27) <= ex6_mvdat_so (1 to 27) & ex6_flag_so (0) ;
|
|
fpscr_th0_si (0 to 27) <= fpscr_th0_so (1 to 27) & ex6_mvdat_so (0) ;
|
|
fpscr_th1_si (0 to 27) <= fpscr_th1_so (1 to 27) & fpscr_th0_so (0) ;
|
|
fpscr_th2_si (0 to 27) <= fpscr_th2_so (1 to 27) & fpscr_th1_so (0) ;
|
|
fpscr_th3_si (0 to 27) <= fpscr_th3_so (1 to 27) & fpscr_th2_so (0) ;
|
|
ex7_crf_si (0 to 3) <= ex7_crf_so (1 to 3) & fpscr_th3_so (0) ;
|
|
act_si (0 to 13) <= act_so (1 to 13) & ex7_crf_so (0) ;
|
|
f_scr_so <= act_so (0) ;
|
|
|
|
|
|
unused_stuff <=
|
|
or_reduce( f_nrm_ex5_fpscr_wr_dat(24 to 31) ) or
|
|
ex6_mtfsbx or
|
|
ex6_fpscr_move(1) or
|
|
ex6_fpscr_move(2) or
|
|
ex6_fpscr_move(20) or
|
|
ex6_fpscr_pipe(1) or
|
|
ex6_fpscr_pipe(2) or
|
|
ex6_fpscr_pipe(20) or
|
|
ex6_mv_data(1) or
|
|
ex6_mv_data(2) or
|
|
ex6_mv_sel(1) or
|
|
ex6_mv_sel(2) ;
|
|
|
|
end; -- fuq_scr ARCHITECTURE
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