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94 lines
3.6 KiB
VHDL
94 lines
3.6 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--********************************************************************
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--*
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--* TITLE: IU Branch Decode
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--*
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--* NAME: iuq_bd.vhdl
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--*
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--*********************************************************************
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library ieee, ibm, support;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_support.all;
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entity iuq_bd is
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port(
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instruction : in std_ulogic_vector(0 to 31);
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branch_decode : out std_ulogic_vector(0 to 3);
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bp_bc_en : in std_ulogic;
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bp_bclr_en : in std_ulogic;
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bp_bcctr_en : in std_ulogic;
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bp_sw_en : in std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end iuq_bd;
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----
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architecture iuq_bd of iuq_bd is
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signal b : std_ulogic;
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signal bc : std_ulogic;
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signal bclr : std_ulogic;
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signal bcctr : std_ulogic;
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signal br_val : std_ulogic;
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signal bo : std_ulogic_vector(0 to 4);
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signal hint : std_ulogic;
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signal hint_val : std_ulogic;
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signal unused_instruction : std_ulogic_vector(0 to 10);
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begin
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unused_instruction <= instruction(11 to 20) & instruction(31);
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b <= instruction(0 to 5) = "010010";
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bc <= bp_bc_en and instruction(0 to 5) = "010000";
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bclr <= bp_bclr_en and instruction(0 to 5) = "010011" and instruction(21 to 30) = "0000010000";
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bcctr <= bp_bcctr_en and instruction(0 to 5) = "010011" and instruction(21 to 30) = "1000010000";
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br_val <= b or bc or bclr or bcctr;
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bo(0 to 4) <= instruction(6 to 10);
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hint_val <= (bo(0) and bo(2)) or (bp_sw_en and ((bo(0) = '0' and bo(2) = '1' and bo(3) = '1') or
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(bo(0) = '1' and bo(2) = '0' and bo(1) = '1')));
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hint <= (bo(0) and bo(2)) or bo(4);
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branch_decode(0 to 3) <= br_val & b & hint_val & hint;
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end iuq_bd;
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