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360 lines
14 KiB
VHDL
360 lines
14 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--********************************************************************
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--*
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--* TITLE: debug event mux
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--*
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--* NAME: iuq_dbg.vhdl
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--*
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--*********************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm,clib;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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library work;
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use work.iuq_pkg.all;
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entity iuq_dbg is
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generic(expand_type : integer := 2 );
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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pc_iu_func_slp_sl_thold_2 : in std_ulogic;
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pc_iu_sg_2 : in std_ulogic;
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clkoff_b : in std_ulogic;
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act_dis : in std_ulogic;
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tc_ac_ccflush_dc : in std_ulogic;
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d_mode : in std_ulogic;
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delay_lclkr : in std_ulogic;
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mpw1_b : in std_ulogic;
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mpw2_b : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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fiss_dbg_data : in std_ulogic_vector(0 to 87);
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fdep_dbg_data : in std_ulogic_vector(0 to 87);
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ib_dbg_data : in std_ulogic_vector(0 to 63);
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bp_dbg_data0 : in std_ulogic_vector(0 to 87);
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bp_dbg_data1 : in std_ulogic_vector(0 to 87);
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fu_iss_dbg_data : in std_ulogic_vector(0 to 23);
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axu_dbg_data_t0 : in std_ulogic_vector(0 to 37);
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axu_dbg_data_t1 : in std_ulogic_vector(0 to 37);
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axu_dbg_data_t2 : in std_ulogic_vector(0 to 37);
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axu_dbg_data_t3 : in std_ulogic_vector(0 to 37);
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bht_dbg_data : in std_ulogic_vector(0 to 31);
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pc_iu_trace_bus_enable : in std_ulogic;
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pc_iu_debug_mux_ctrls : in std_ulogic_vector(0 to 15);
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debug_data_in : in std_ulogic_vector(0 to 87);
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trace_triggers_in : in std_ulogic_vector(0 to 11);
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debug_data_out : out std_ulogic_vector(0 to 87);
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trace_triggers_out : out std_ulogic_vector(0 to 11)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end iuq_dbg;
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architecture iuq_dbg of iuq_dbg is
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signal trigger_data_out_d : std_ulogic_vector(0 to 11);
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signal trigger_data_out_q : std_ulogic_vector(0 to 11);
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signal trace_data_out_d : std_ulogic_vector(0 to 87);
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signal trace_data_out_q : std_ulogic_vector(0 to 87);
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constant trigger_data_out_offset: natural := 0;
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constant trace_data_out_offset : natural := trigger_data_out_offset + trigger_data_out_q'length;
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constant trace_bus_enable_offset: natural := trace_data_out_offset + trace_data_out_q'length;
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constant debug_mux_ctrls_offset : natural := trace_bus_enable_offset + 1;
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constant scan_right : natural := debug_mux_ctrls_offset + 16-1;
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signal dbg_group0 : std_ulogic_vector(0 to 87);
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signal dbg_group1 : std_ulogic_vector(0 to 87);
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signal dbg_group2 : std_ulogic_vector(0 to 87);
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signal dbg_group3 : std_ulogic_vector(0 to 87);
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signal dbg_group4 : std_ulogic_vector(0 to 87);
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signal dbg_group5 : std_ulogic_vector(0 to 87);
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signal dbg_group6 : std_ulogic_vector(0 to 87);
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signal dbg_group7 : std_ulogic_vector(0 to 87);
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signal trg_group0 : std_ulogic_vector(0 to 11);
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signal trg_group1 : std_ulogic_vector(0 to 11);
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signal trg_group2 : std_ulogic_vector(0 to 11);
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signal trg_group3 : std_ulogic_vector(0 to 11);
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signal siv : std_ulogic_vector(0 to scan_right);
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signal sov : std_ulogic_vector(0 to scan_right);
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signal tiup : std_ulogic;
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signal pc_iu_func_slp_sl_thold_1 : std_ulogic;
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signal pc_iu_func_slp_sl_thold_0 : std_ulogic;
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signal pc_iu_func_slp_sl_thold_0_b : std_ulogic;
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signal pc_iu_sg_1 : std_ulogic;
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signal pc_iu_sg_0 : std_ulogic;
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signal forcee : std_ulogic;
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signal trace_bus_enable_d : std_ulogic;
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signal trace_bus_enable_q : std_ulogic;
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signal debug_mux_ctrls_d : std_ulogic_vector(0 to 15);
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signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15);
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begin
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-----------------------------------------------------------------------
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-- Logic
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-----------------------------------------------------------------------
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tiup <= '1';
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dbg_group0 <= bp_dbg_data0(0 to 87);
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dbg_group1 <= bp_dbg_data1(0 to 87);
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dbg_group2 <= ib_dbg_data(0 to 63) & fu_iss_dbg_data(0 to 23);
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dbg_group3 <= fdep_dbg_data(0 to 87);
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dbg_group4 <= fiss_dbg_data(0 to 87);
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dbg_group5(0 to 75) <= axu_dbg_data_t0(0 to 37) & axu_dbg_data_t1(0 to 37);
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dbg_group6(0 to 75) <= axu_dbg_data_t2(0 to 37) & axu_dbg_data_t3(0 to 37);
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dbg_group7(0 to 31) <= bht_dbg_data(0 to 31);
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dbg_group5(76 to 87) <= (others => '0');
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dbg_group6(76 to 87) <= (others => '0');
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dbg_group7(32 to 87) <= (others => '0');
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trg_group0 <= ib_dbg_data(0) & ib_dbg_data( 4 to 5) & --t0: bp_val, rm_val, uc_val
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ib_dbg_data(16) & ib_dbg_data(20 to 21) & --t1
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ib_dbg_data(32) & ib_dbg_data(36 to 37) & --t2
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ib_dbg_data(48) & ib_dbg_data(52 to 53) ; --t3
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trg_group1 <= fiss_dbg_data(0 to 7) & --high pri mask(0 to 3), low pri mask (0 to 3)
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fiss_dbg_data(44 to 45) & --is2 instr_val, uc_val
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bp_dbg_data0(84 to 85); --ex6 val, br_update
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trg_group2 <= fdep_dbg_data(14) & fdep_dbg_data(36) & fdep_dbg_data(58) & fdep_dbg_data(80) & --is1 val
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bht_dbg_data(27 to 31) & --r_act, w_act(0 to 3)
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bp_dbg_data1(84 to 86) ; --ex6 br_taken, bclr, lk
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trg_group3 <= axu_dbg_data_t0(10) & -- 0 is1_to_ucode
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axu_dbg_data_t1(10) & -- 1 is1_to_ucode
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axu_dbg_data_t2(10) & -- 2 is1_to_ucode
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axu_dbg_data_t3(10) & -- 3 is1_to_ucode
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axu_dbg_data_t0(21) & -- 4 bubble3_is1_db
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axu_dbg_data_t1(21) & -- 5 bubble3_is1_db
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axu_dbg_data_t2(21) & -- 6 bubble3_is1_db
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axu_dbg_data_t3(21) & -- 7 bubble3_is1_db
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fu_iss_dbg_data(20) & -- 8 is2_issue_sel_db(0)
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fu_iss_dbg_data(21) & -- 9 is2_issue_sel_db(1)
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fu_iss_dbg_data(22) & -- 10 is2_issue_sel_db(2)
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fu_iss_dbg_data(23) ; -- 11 is2_issue_sel_db(3)
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dbg_mux0: entity clib.c_debug_mux8
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port map(
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vd => vdd,
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gd => gnd,
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select_bits => debug_mux_ctrls_q,
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trace_data_in => debug_data_in,
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trigger_data_in => trace_triggers_in,
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dbg_group0 => dbg_group0,
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dbg_group1 => dbg_group1,
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dbg_group2 => dbg_group2,
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dbg_group3 => dbg_group3,
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dbg_group4 => dbg_group4,
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dbg_group5 => dbg_group5,
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dbg_group6 => dbg_group6,
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dbg_group7 => dbg_group7,
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trg_group0 => trg_group0,
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trg_group1 => trg_group1,
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trg_group2 => trg_group2,
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trg_group3 => trg_group3,
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trace_data_out => trace_data_out_d,
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trigger_data_out=> trigger_data_out_d
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);
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trace_triggers_out <= trigger_data_out_q;
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debug_data_out <= trace_data_out_q;
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-----------------------------------------------------------------------
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-- Latches
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-----------------------------------------------------------------------
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trace_bus_enable_d <= pc_iu_trace_bus_enable;
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debug_mux_ctrls_d <= pc_iu_debug_mux_ctrls;
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trace_enable_reg: tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_iu_func_slp_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(trace_bus_enable_offset),
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scout => sov(trace_bus_enable_offset),
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din => trace_bus_enable_d,
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dout => trace_bus_enable_q);
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debug_mux_ctrls_reg: tri_rlmreg_p
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generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => trace_bus_enable_q,
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thold_b => pc_iu_func_slp_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1),
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scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1),
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din => debug_mux_ctrls_d,
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dout => debug_mux_ctrls_q);
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trigger_data_reg: tri_rlmreg_p
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generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => trace_bus_enable_q,
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thold_b => pc_iu_func_slp_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1),
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scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1),
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din => trigger_data_out_d,
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dout => trigger_data_out_q);
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trace_data_reg: tri_rlmreg_p
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generic map (width => trace_data_out_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => trace_bus_enable_q,
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thold_b => pc_iu_func_slp_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1),
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scout => sov(trace_data_out_offset to trace_data_out_offset + trace_data_out_q'length-1),
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din => trace_data_out_d,
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dout => trace_data_out_q);
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-------------------------------------------------
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-- pervasive
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-------------------------------------------------
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perv_2to1_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_func_slp_sl_thold_2,
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din(1) => pc_iu_sg_2,
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q(0) => pc_iu_func_slp_sl_thold_1,
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q(1) => pc_iu_sg_1);
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perv_1to0_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_func_slp_sl_thold_1,
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din(1) => pc_iu_sg_1,
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q(0) => pc_iu_func_slp_sl_thold_0,
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q(1) => pc_iu_sg_0);
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perv_lcbor: tri_lcbor
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generic map (expand_type => expand_type)
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port map (clkoff_b => clkoff_b,
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thold => pc_iu_func_slp_sl_thold_0,
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sg => pc_iu_sg_0,
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act_dis => act_dis,
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forcee => forcee,
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thold_b => pc_iu_func_slp_sl_thold_0_b);
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-----------------------------------------------------------------------
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-- Scan
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-----------------------------------------------------------------------
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siv(0 to scan_right) <= sov(1 to scan_right) & scan_in;
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scan_out <= sov(0);
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end iuq_dbg;
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