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421 lines
16 KiB
VHDL
421 lines
16 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--********************************************************************
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--*
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--* TITLE: Performance event mux
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--*
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--* NAME: iuq_perf.vhdl
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--*
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--*********************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm,clib;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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library work;
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use work.iuq_pkg.all;
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entity iuq_perf is
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generic(expand_type : integer := 2 );
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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pc_iu_func_sl_thold_2 : in std_ulogic;
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pc_iu_sg_2 : in std_ulogic;
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clkoff_b : in std_ulogic;
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act_dis : in std_ulogic;
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tc_ac_ccflush_dc : in std_ulogic;
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d_mode : in std_ulogic;
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delay_lclkr : in std_ulogic;
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mpw1_b : in std_ulogic;
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mpw2_b : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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xu_iu_msr_gs : in std_ulogic_vector(0 to 3);
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xu_iu_msr_pr : in std_ulogic_vector(0 to 3);
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ic_perf_event_t0 : in std_ulogic_vector(0 to 6);
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ic_perf_event_t1 : in std_ulogic_vector(0 to 6);
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ic_perf_event_t2 : in std_ulogic_vector(0 to 6);
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ic_perf_event_t3 : in std_ulogic_vector(0 to 6);
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ic_perf_event : in std_ulogic_vector(0 to 1);
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ib_perf_event_t0 : in std_ulogic_vector(0 to 1);
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ib_perf_event_t1 : in std_ulogic_vector(0 to 1);
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ib_perf_event_t2 : in std_ulogic_vector(0 to 1);
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ib_perf_event_t3 : in std_ulogic_vector(0 to 1);
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fdep_perf_event_t0 : in std_ulogic_vector(0 to 11);
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fdep_perf_event_t1 : in std_ulogic_vector(0 to 11);
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fdep_perf_event_t2 : in std_ulogic_vector(0 to 11);
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fdep_perf_event_t3 : in std_ulogic_vector(0 to 11);
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fiss_perf_event_t0 : in std_ulogic_vector(0 to 7);
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fiss_perf_event_t1 : in std_ulogic_vector(0 to 7);
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fiss_perf_event_t2 : in std_ulogic_vector(0 to 7);
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fiss_perf_event_t3 : in std_ulogic_vector(0 to 7);
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pc_iu_event_mux_ctrls : in std_ulogic_vector(0 to 47);
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pc_iu_event_count_mode : in std_ulogic_vector(0 to 2);
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pc_iu_event_bus_enable : in std_ulogic;
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iu_pc_event_data : out std_ulogic_vector(0 to 7)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end iuq_perf;
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architecture iuq_perf of iuq_perf is
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constant event_data_offset : natural := 0;
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constant event_count_mode_offset: natural := event_data_offset + 8;
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constant xu_iu_msr_gs_offset : natural := event_count_mode_offset + 3;
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constant xu_iu_msr_pr_offset : natural := xu_iu_msr_gs_offset + 4;
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constant event_bus_enable_offset: natural := xu_iu_msr_pr_offset + 4;
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constant event_mux_ctrls_offset : natural := event_bus_enable_offset + 1;
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constant scan_right : natural := event_mux_ctrls_offset + 48-1;
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signal event_data_d : std_ulogic_vector(0 to 7);
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signal event_data_q : std_ulogic_vector(0 to 7);
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signal t0_events : std_ulogic_vector(0 to 31);
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signal t1_events : std_ulogic_vector(0 to 31);
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signal t2_events : std_ulogic_vector(0 to 31);
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signal t3_events : std_ulogic_vector(0 to 31);
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signal xu_iu_msr_gs_d : std_ulogic_vector(0 to 3);
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signal xu_iu_msr_gs_q : std_ulogic_vector(0 to 3);
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signal xu_iu_msr_pr_d : std_ulogic_vector(0 to 3);
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signal xu_iu_msr_pr_q : std_ulogic_vector(0 to 3);
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signal event_count_mode_d : std_ulogic_vector(0 to 2);
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signal event_count_mode_q : std_ulogic_vector(0 to 2);
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signal event_en : std_ulogic_vector(0 to 3);
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signal siv : std_ulogic_vector(0 to scan_right);
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signal sov : std_ulogic_vector(0 to scan_right);
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signal tiup : std_ulogic;
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signal pc_iu_func_sl_thold_1 : std_ulogic;
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signal pc_iu_func_sl_thold_0 : std_ulogic;
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signal pc_iu_func_sl_thold_0_b : std_ulogic;
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signal pc_iu_sg_1 : std_ulogic;
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signal pc_iu_sg_0 : std_ulogic;
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signal forcee : std_ulogic;
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signal event_bus_enable_d : std_ulogic;
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signal event_bus_enable_q : std_ulogic;
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signal event_mux_ctrls_d : std_ulogic_vector(0 to 47);
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signal event_mux_ctrls_q : std_ulogic_vector(0 to 47);
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begin
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-----------------------------------------------------------------------
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-- Logic
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-----------------------------------------------------------------------
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tiup <= '1';
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----------------------------------------------------
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-- t* event list
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----------------------------------------------------
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-- 0 IL1 miss cycles
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-- 1 IL1 reloads dropped
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-- 2 reload collisions
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-- 3 iu0 redirect
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-- 4 ierat miss
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-- 5 icache fetch
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-- 6 instructions fetched
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-- 7 reserved
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-- 8 l2 back invalidates icache
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-- 9 l2 back invalidates icache hits
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-- 10 ibuff empty
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-- 11 ibuff flush
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-- 12 is1 stall
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-- 13 is2 stall
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-- 14 barrier stall
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-- 15 slowspr stall
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-----
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-- 16 raw dep hit
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-- 17 waw dep hit
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-- 18 sync dep hit
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-- 19 spr dep hit
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-- 20 axu dep hit
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-- 21 fxu dep hit
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-- 22 axu/fxu dep hit
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-- 23 reserved
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-- 24 2 instr issue
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-- 25 axu priority loss
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-- 26 fxu priority loss
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-- 27 axu issue
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-- 28 fxu issue
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-- 29 total issue
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-- 30 instruction match issue
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-- 31 reserved
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----------------------------------------------------
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xu_iu_msr_gs_d <= xu_iu_msr_gs;
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xu_iu_msr_pr_d <= xu_iu_msr_pr;
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event_count_mode_d <= pc_iu_event_count_mode;
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event_en(0 to 3) <= gate( xu_iu_msr_pr_q(0 to 3) , event_count_mode_q(0)) or -- User
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gate(not xu_iu_msr_pr_q(0 to 3) and xu_iu_msr_gs_q(0 to 3), event_count_mode_q(1)) or -- Guest Supervisor
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gate(not xu_iu_msr_pr_q(0 to 3) and not xu_iu_msr_gs_q(0 to 3), event_count_mode_q(2)); -- Hypervisor
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t0_events(0 to 31) <= gate(
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ic_perf_event_t0(0 to 6) & '0' &
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ic_perf_event(0 to 1) &
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ib_perf_event_t0(0 to 1) &
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fdep_perf_event_t0(0 to 11) &
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fiss_perf_event_t0(0 to 7),
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event_en(0));
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t1_events(0 to 31) <= gate(
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ic_perf_event_t1(0 to 6) & '0' &
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ic_perf_event(0 to 1) &
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ib_perf_event_t1(0 to 1) &
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fdep_perf_event_t1(0 to 11) &
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fiss_perf_event_t1(0 to 7),
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event_en(1));
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t2_events(0 to 31) <= gate(
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ic_perf_event_t2(0 to 6) & '0' &
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ic_perf_event(0 to 1) &
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ib_perf_event_t2(0 to 1) &
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fdep_perf_event_t2(0 to 11) &
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fiss_perf_event_t2(0 to 7),
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event_en(2));
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t3_events(0 to 31) <= gate(
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ic_perf_event_t3(0 to 6) & '0' &
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ic_perf_event(0 to 1) &
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ib_perf_event_t3(0 to 1) &
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fdep_perf_event_t3(0 to 11) &
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fiss_perf_event_t3(0 to 7),
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event_en(3));
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event_mux1: entity clib.c_event_mux
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generic map ( events_in => 128 )
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port map(vd => vdd,
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gd => gnd,
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t0_events => t0_events(0 to 31),
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t1_events => t1_events(0 to 31),
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t2_events => t2_events(0 to 31),
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t3_events => t3_events(0 to 31),
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select_bits => event_mux_ctrls_q(0 to 47),
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event_bits => event_data_d(0 to 7)
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);
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iu_pc_event_data <= event_data_q(0 to 7);
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-----------------------------------------------------------------------
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-- Latches
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-----------------------------------------------------------------------
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event_bus_enable_d <= pc_iu_event_bus_enable;
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event_mux_ctrls_d <= pc_iu_event_mux_ctrls;
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event_enable_reg: tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(event_bus_enable_offset),
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scout => sov(event_bus_enable_offset),
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din => event_bus_enable_d,
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dout => event_bus_enable_q);
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event_mux_ctrls_reg: tri_rlmreg_p
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generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => event_bus_enable_q,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1),
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scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1),
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din => event_mux_ctrls_d,
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dout => event_mux_ctrls_q);
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event_data_reg: tri_rlmreg_p
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generic map (width => event_data_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => event_bus_enable_q,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(event_data_offset to event_data_offset + event_data_q'length-1),
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scout => sov(event_data_offset to event_data_offset + event_data_q'length-1),
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din => event_data_d,
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dout => event_data_q);
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event_count_mode_reg: tri_rlmreg_p
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generic map (width => event_count_mode_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => event_bus_enable_q,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(event_count_mode_offset to event_count_mode_offset + event_count_mode_q'length-1),
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scout => sov(event_count_mode_offset to event_count_mode_offset + event_count_mode_q'length-1),
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din => event_count_mode_d,
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dout => event_count_mode_q);
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xu_iu_msr_gs_reg: tri_rlmreg_p
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generic map (width => xu_iu_msr_gs_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => event_bus_enable_q,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_q'length-1),
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scout => sov(xu_iu_msr_gs_offset to xu_iu_msr_gs_offset + xu_iu_msr_gs_q'length-1),
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din => xu_iu_msr_gs_d,
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dout => xu_iu_msr_gs_q);
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xu_iu_msr_pr_reg: tri_rlmreg_p
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generic map (width => xu_iu_msr_pr_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => event_bus_enable_q,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_q'length-1),
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scout => sov(xu_iu_msr_pr_offset to xu_iu_msr_pr_offset + xu_iu_msr_pr_q'length-1),
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din => xu_iu_msr_pr_d,
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dout => xu_iu_msr_pr_q);
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-------------------------------------------------
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-- pervasive
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-------------------------------------------------
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perv_2to1_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_func_sl_thold_2,
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din(1) => pc_iu_sg_2,
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q(0) => pc_iu_func_sl_thold_1,
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q(1) => pc_iu_sg_1);
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perv_1to0_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_func_sl_thold_1,
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din(1) => pc_iu_sg_1,
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q(0) => pc_iu_func_sl_thold_0,
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q(1) => pc_iu_sg_0);
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perv_lcbor: tri_lcbor
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generic map (expand_type => expand_type)
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port map (clkoff_b => clkoff_b,
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thold => pc_iu_func_sl_thold_0,
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sg => pc_iu_sg_0,
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act_dis => act_dis,
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forcee => forcee,
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thold_b => pc_iu_func_sl_thold_0_b);
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-----------------------------------------------------------------------
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-- Scan
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-----------------------------------------------------------------------
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siv(0 to scan_right) <= sov(1 to scan_right) & scan_in;
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scan_out <= sov(0);
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end iuq_perf;
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