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355 lines
14 KiB
VHDL
355 lines
14 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity iuq_perv is
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generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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pc_iu_sg_3 : in std_ulogic_vector(0 to 3);
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pc_iu_func_sl_thold_3 : in std_ulogic_vector(0 to 3);
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pc_iu_func_slp_sl_thold_3 : in std_ulogic;
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pc_iu_gptr_sl_thold_3 : in std_ulogic;
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pc_iu_time_sl_thold_3 : in std_ulogic;
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pc_iu_repr_sl_thold_3 : in std_ulogic;
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pc_iu_abst_sl_thold_3 : in std_ulogic;
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pc_iu_abst_slp_sl_thold_3 : in std_ulogic;
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pc_iu_cfg_sl_thold_3 : in std_ulogic;
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pc_iu_cfg_slp_sl_thold_3 : in std_ulogic;
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pc_iu_regf_slp_sl_thold_3 : in std_ulogic;
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pc_iu_ary_nsl_thold_3 : in std_ulogic;
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pc_iu_ary_slp_nsl_thold_3 : in std_ulogic;
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pc_iu_func_slp_nsl_thold_3 : in std_ulogic;
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pc_iu_bolt_sl_thold_3 : in std_ulogic;
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pc_iu_bo_enable_3 : in std_ulogic;
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pc_iu_fce_3 : in std_ulogic;
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tc_ac_ccflush_dc : in std_ulogic;
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scan_diag_dc : in std_ulogic;
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pc_iu_sg_2 : out std_ulogic_vector(0 to 3);
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pc_iu_func_sl_thold_2 : out std_ulogic_vector(0 to 3);
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pc_iu_func_slp_sl_thold_2 : out std_ulogic;
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pc_iu_time_sl_thold_2 : out std_ulogic;
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pc_iu_repr_sl_thold_2 : out std_ulogic;
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pc_iu_abst_sl_thold_2 : out std_ulogic;
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pc_iu_abst_slp_sl_thold_2 : out std_ulogic;
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pc_iu_cfg_sl_thold_2 : out std_ulogic;
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pc_iu_cfg_slp_sl_thold_2 : out std_ulogic;
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pc_iu_regf_slp_sl_thold_2 : out std_ulogic;
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pc_iu_ary_nsl_thold_2 : out std_ulogic;
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pc_iu_ary_slp_nsl_thold_2 : out std_ulogic;
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pc_iu_func_slp_nsl_thold_2 : out std_ulogic;
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pc_iu_bolt_sl_thold_2 : out std_ulogic;
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pc_iu_bo_enable_2 : out std_ulogic;
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pc_iu_fce_2 : out std_ulogic;
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clkoff_b : out std_ulogic_vector(0 to 2);
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act_dis : out std_ulogic_vector(0 to 2);
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d_mode : out std_ulogic_vector(0 to 2);
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delay_lclkr : out std_ulogic_vector(0 to 14);
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mpw1_b : out std_ulogic_vector(0 to 14);
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mpw2_b : out std_ulogic_vector(0 to 2);
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bht_g8t_clkoff_b : out std_ulogic;
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bht_g8t_d_mode : out std_ulogic;
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bht_g8t_delay_lclkr : out std_ulogic_vector(0 to 4);
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bht_g8t_mpw1_b : out std_ulogic_vector(0 to 4);
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bht_g8t_mpw2_b : out std_ulogic;
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g8t_clkoff_b : out std_ulogic;
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g8t_d_mode : out std_ulogic;
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g8t_delay_lclkr : out std_ulogic_vector(0 to 4);
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g8t_mpw1_b : out std_ulogic_vector(0 to 4);
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g8t_mpw2_b : out std_ulogic;
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g6t_clkoff_b : out std_ulogic;
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g6t_d_mode : out std_ulogic;
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g6t_delay_lclkr : out std_ulogic_vector(0 to 3);
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g6t_mpw1_b : out std_ulogic_vector(0 to 4);
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g6t_mpw2_b : out std_ulogic;
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cam_clkoff_b : out std_ulogic;
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cam_d_mode : out std_ulogic;
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cam_delay_lclkr : out std_ulogic_vector(0 to 4);
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cam_mpw1_b : out std_ulogic_vector(0 to 4);
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cam_mpw2_b : out std_ulogic;
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gptr_scan_in : in std_ulogic;
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gptr_scan_out : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end iuq_perv;
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architecture iuq_perv of iuq_perv is
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signal pc_iu_gptr_sl_thold_2_int : std_ulogic;
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signal pc_iu_time_sl_thold_2_int : std_ulogic;
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signal pc_iu_sg_2_int : std_ulogic_vector(0 to 3);
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signal pc_iu_gptr_sl_thold_1 : std_ulogic;
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signal pc_iu_sg_1 : std_ulogic;
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signal pc_iu_gptr_sl_thold_0 : std_ulogic;
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signal pc_iu_sg_0 : std_ulogic;
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signal int_g6t_delay_lclkr : std_ulogic_vector(0 to 4);
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signal unused : std_ulogic;
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-- synopsys translate_off
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-- synopsys translate_on
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signal gptr_siv : std_ulogic_vector(0 to 6);
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signal gptr_sov : std_ulogic_vector(0 to 6);
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begin
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perv_3to2_reg: tri_plat
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generic map (width => 23, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0 to 3) => pc_iu_func_sl_thold_3(0 to 3),
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din(4) => pc_iu_gptr_sl_thold_3,
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din(5) => pc_iu_time_sl_thold_3,
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din(6) => pc_iu_repr_sl_thold_3,
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din(7) => pc_iu_abst_sl_thold_3,
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din(8) => pc_iu_ary_nsl_thold_3,
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din(9 to 12) => pc_iu_sg_3(0 to 3),
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din(13) => pc_iu_fce_3,
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din(14) => pc_iu_cfg_slp_sl_thold_3,
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din(15) => pc_iu_cfg_sl_thold_3,
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din(16) => pc_iu_regf_slp_sl_thold_3,
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din(17) => pc_iu_func_slp_sl_thold_3,
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din(18) => pc_iu_ary_slp_nsl_thold_3,
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din(19) => pc_iu_abst_slp_sl_thold_3,
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din(20) => pc_iu_func_slp_nsl_thold_3,
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din(21) => pc_iu_bolt_sl_thold_3,
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din(22) => pc_iu_bo_enable_3,
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q(0 to 3) => pc_iu_func_sl_thold_2(0 to 3),
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q(4) => pc_iu_gptr_sl_thold_2_int,
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q(5) => pc_iu_time_sl_thold_2_int,
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q(6) => pc_iu_repr_sl_thold_2,
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q(7) => pc_iu_abst_sl_thold_2,
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q(8) => pc_iu_ary_nsl_thold_2,
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q(9 to 12) => pc_iu_sg_2_int(0 to 3),
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q(13) => pc_iu_fce_2,
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q(14) => pc_iu_cfg_slp_sl_thold_2,
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q(15) => pc_iu_cfg_sl_thold_2,
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q(16) => pc_iu_regf_slp_sl_thold_2,
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q(17) => pc_iu_func_slp_sl_thold_2,
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q(18) => pc_iu_ary_slp_nsl_thold_2,
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q(19) => pc_iu_abst_slp_sl_thold_2,
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q(20) => pc_iu_func_slp_nsl_thold_2,
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q(21) => pc_iu_bolt_sl_thold_2,
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q(22) => pc_iu_bo_enable_2);
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pc_iu_time_sl_thold_2 <= pc_iu_time_sl_thold_2_int;
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pc_iu_sg_2 <= pc_iu_sg_2_int;
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perv_2to1_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_gptr_sl_thold_2_int,
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din(1) => pc_iu_sg_2_int(0),
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q(0) => pc_iu_gptr_sl_thold_1,
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q(1) => pc_iu_sg_1);
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perv_1to0_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_gptr_sl_thold_1,
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din(1) => pc_iu_sg_1,
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q(0) => pc_iu_gptr_sl_thold_0,
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q(1) => pc_iu_sg_0);
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perv_lcbcntl0: tri_lcbcntl_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => pc_iu_sg_0,
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nclk => nclk,
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scan_in => gptr_siv(0),
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scan_diag_dc => scan_diag_dc,
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thold => pc_iu_gptr_sl_thold_0,
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clkoff_dc_b => clkoff_b(0),
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delay_lclkr_dc => delay_lclkr(0 to 4),
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act_dis_dc => open,
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d_mode_dc => d_mode(0),
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mpw1_dc_b => mpw1_b(0 to 4),
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mpw2_dc_b => mpw2_b(0),
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scan_out => gptr_sov(0));
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perv_lcbcntl1: tri_lcbcntl_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => pc_iu_sg_0,
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nclk => nclk,
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scan_in => gptr_siv(1),
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scan_diag_dc => scan_diag_dc,
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thold => pc_iu_gptr_sl_thold_0,
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clkoff_dc_b => clkoff_b(1),
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delay_lclkr_dc => delay_lclkr(5 to 9),
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act_dis_dc => open,
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d_mode_dc => d_mode(1),
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mpw1_dc_b => mpw1_b(5 to 9),
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mpw2_dc_b => mpw2_b(1),
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scan_out => gptr_sov(1));
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perv_lcbcntl2: tri_lcbcntl_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => pc_iu_sg_0,
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nclk => nclk,
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scan_in => gptr_siv(2),
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scan_diag_dc => scan_diag_dc,
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thold => pc_iu_gptr_sl_thold_0,
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clkoff_dc_b => clkoff_b(2),
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delay_lclkr_dc => delay_lclkr(10 to 14),
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act_dis_dc => open,
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d_mode_dc => d_mode(2),
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mpw1_dc_b => mpw1_b(10 to 14),
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mpw2_dc_b => mpw2_b(2),
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scan_out => gptr_sov(2));
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perv_lcbcntl_g8t_bht: tri_lcbcntl_array_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => pc_iu_sg_0,
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nclk => nclk,
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scan_in => gptr_siv(3),
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scan_diag_dc => scan_diag_dc,
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thold => pc_iu_gptr_sl_thold_0,
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clkoff_dc_b => bht_g8t_clkoff_b,
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delay_lclkr_dc => bht_g8t_delay_lclkr(0 to 4),
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act_dis_dc => open,
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d_mode_dc => bht_g8t_d_mode,
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mpw1_dc_b => bht_g8t_mpw1_b(0 to 4),
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mpw2_dc_b => bht_g8t_mpw2_b,
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scan_out => gptr_sov(3));
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perv_lcbcntl_g8t: tri_lcbcntl_array_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => pc_iu_sg_0,
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nclk => nclk,
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scan_in => gptr_siv(4),
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scan_diag_dc => scan_diag_dc,
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thold => pc_iu_gptr_sl_thold_0,
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clkoff_dc_b => g8t_clkoff_b,
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delay_lclkr_dc => g8t_delay_lclkr(0 to 4),
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act_dis_dc => open,
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d_mode_dc => g8t_d_mode,
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mpw1_dc_b => g8t_mpw1_b(0 to 4),
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mpw2_dc_b => g8t_mpw2_b,
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scan_out => gptr_sov(4));
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perv_lcbcntl_g6t: tri_lcbcntl_array_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => pc_iu_sg_0,
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nclk => nclk,
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scan_in => gptr_siv(5),
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scan_diag_dc => scan_diag_dc,
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thold => pc_iu_gptr_sl_thold_0,
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clkoff_dc_b => g6t_clkoff_b,
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delay_lclkr_dc => int_g6t_delay_lclkr,
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act_dis_dc => open,
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d_mode_dc => g6t_d_mode,
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mpw1_dc_b => g6t_mpw1_b(0 to 4),
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mpw2_dc_b => g6t_mpw2_b,
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scan_out => gptr_sov(5));
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perv_lcbcntl_cam: tri_lcbcntl_array_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => pc_iu_sg_0,
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nclk => nclk,
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scan_in => gptr_siv(6),
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scan_diag_dc => scan_diag_dc,
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thold => pc_iu_gptr_sl_thold_0,
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clkoff_dc_b => cam_clkoff_b,
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delay_lclkr_dc => cam_delay_lclkr(0 to 4),
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act_dis_dc => open,
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d_mode_dc => cam_d_mode,
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mpw1_dc_b => cam_mpw1_b(0 to 4),
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mpw2_dc_b => cam_mpw2_b,
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scan_out => gptr_sov(6));
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g6t_delay_lclkr <= int_g6t_delay_lclkr(0 to 3);
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unused <= int_g6t_delay_lclkr(4);
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--never disable act pins, they are used functionally
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act_dis(0 to 2) <= "000";
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-----------------------------------------------------------------------
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-- Scan
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-----------------------------------------------------------------------
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gptr_siv(0 to 6) <= gptr_sov(1 to 6) & gptr_scan_in;
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gptr_scan_out <= gptr_sov(0);
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end iuq_perv;
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