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277 lines
9.5 KiB
VHDL
277 lines
9.5 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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library work;
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use work.iuq_pkg.all;
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entity iuq_ram is
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generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
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port(
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pc_iu_ram_instr : in std_ulogic_vector(0 to 31);
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pc_iu_ram_instr_ext : in std_ulogic_vector(0 to 3);
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pc_iu_ram_force_cmplt : in std_ulogic;
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xu_iu_ram_issue : in std_ulogic_vector(0 to 3);
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rm_ib_iu4_val : out std_ulogic_vector(0 to 3);
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rm_ib_iu4_force_ram : out std_ulogic;
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rm_ib_iu4_instr : out std_ulogic_vector(0 to 35);
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--pervasive
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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pc_iu_sg_2 : in std_ulogic;
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pc_iu_func_sl_thold_2 : in std_ulogic;
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clkoff_b : in std_ulogic;
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act_dis : in std_ulogic;
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tc_ac_ccflush_dc : in std_ulogic;
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d_mode : in std_ulogic;
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delay_lclkr : in std_ulogic;
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mpw1_b : in std_ulogic;
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mpw2_b : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end iuq_ram;
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----
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architecture iuq_ram of iuq_ram is
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----------------------------
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-- constants
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----------------------------
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--scan chain
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constant ram_val_offset : natural := 0;
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constant ram_iss_offset : natural := ram_val_offset + 4;
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constant ram_instr_offset : natural := ram_iss_offset + 4;
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constant ram_force_offset : natural := ram_instr_offset + 36;
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constant scan_right : natural := ram_force_offset + 1-1;
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----------------------------
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-- signals
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----------------------------
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signal tiup : std_ulogic;
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signal ram_valid : std_ulogic;
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signal ram_iss_d : std_ulogic_vector(0 to 3);
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signal ram_iss_q : std_ulogic_vector(0 to 3);
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signal ram_val_d : std_ulogic_vector(0 to 3);
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signal ram_val_q : std_ulogic_vector(0 to 3);
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signal ram_instr_d : std_ulogic_vector(0 to 35);
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signal ram_instr_q : std_ulogic_vector(0 to 35);
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signal ram_force_d : std_ulogic;
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signal ram_force_q : std_ulogic;
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signal pc_iu_func_sl_thold_1 : std_ulogic;
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signal pc_iu_func_sl_thold_0 : std_ulogic;
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signal pc_iu_func_sl_thold_0_b : std_ulogic;
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signal pc_iu_sg_1 : std_ulogic;
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signal pc_iu_sg_0 : std_ulogic;
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signal forcee : std_ulogic;
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signal siv : std_ulogic_vector(0 to scan_right);
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signal sov : std_ulogic_vector(0 to scan_right);
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begin
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tiup <= '1';
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-------------------------------------------------
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-- logic
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-------------------------------------------------
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ram_iss_d <= xu_iu_ram_issue;
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ram_val_d <= ram_iss_q and not ram_iss_d; --detect falling edge of ram issue
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ram_valid <= or_reduce(ram_iss_q);
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ram_instr_d <= pc_iu_ram_instr & pc_iu_ram_instr_ext;
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ram_force_d <= pc_iu_ram_force_cmplt;
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-------------------------------------------------
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-- outputs
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-------------------------------------------------
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rm_ib_iu4_val <= ram_val_q;
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rm_ib_iu4_instr <= ram_instr_q;
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rm_ib_iu4_force_ram <= ram_force_q;
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-------------------------------------------------
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-- latches
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-------------------------------------------------
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ram_iss_reg: tri_rlmreg_p
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generic map (width => 4, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(ram_iss_offset to ram_iss_offset+3),
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scout => sov(ram_iss_offset to ram_iss_offset+3),
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din => ram_iss_d(0 to 3),
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dout => ram_iss_q(0 to 3));
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ram_val_reg: tri_rlmreg_p
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generic map (width => 4, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(ram_val_offset to ram_val_offset+3),
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scout => sov(ram_val_offset to ram_val_offset+3),
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din => ram_val_d(0 to 3),
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dout => ram_val_q(0 to 3));
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ram_instr_reg: tri_rlmreg_p
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generic map (width => 36, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => ram_valid,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(ram_instr_offset to ram_instr_offset+35),
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scout => sov(ram_instr_offset to ram_instr_offset+35),
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din => ram_instr_d(0 to 35),
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dout => ram_instr_q(0 to 35));
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ram_force_reg: tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => ram_valid,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(ram_force_offset),
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scout => sov(ram_force_offset),
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din => ram_force_d,
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dout => ram_force_q);
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-------------------------------------------------
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-- pervasive
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-------------------------------------------------
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perv_2to1_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_func_sl_thold_2,
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din(1) => pc_iu_sg_2,
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q(0) => pc_iu_func_sl_thold_1,
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q(1) => pc_iu_sg_1);
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perv_1to0_reg: tri_plat
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generic map (width => 2, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => tc_ac_ccflush_dc,
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din(0) => pc_iu_func_sl_thold_1,
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din(1) => pc_iu_sg_1,
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q(0) => pc_iu_func_sl_thold_0,
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q(1) => pc_iu_sg_0);
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perv_lcbor: tri_lcbor
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generic map (expand_type => expand_type)
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port map (clkoff_b => clkoff_b,
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thold => pc_iu_func_sl_thold_0,
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sg => pc_iu_sg_0,
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act_dis => act_dis,
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forcee => forcee,
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thold_b => pc_iu_func_sl_thold_0_b);
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-------------------------------------------------
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-- scan
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-------------------------------------------------
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siv(0 to scan_right) <= scan_in & sov(0 to scan_right-1);
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scan_out <= sov(scan_right);
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end iuq_ram;
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