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371 lines
16 KiB
VHDL
371 lines
16 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--********************************************************************
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--*
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--* TITLE: MMU TLB LRAT Match Line Logic for Functional Model
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--*
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--* NAME: mmq_tlb_lrat_matchline
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--*
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LIBRARY IEEE;
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USE ieee.std_logic_1164.ALL ;
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LIBRARY IBM;
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USE ibm.std_ulogic_support.ALL;
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USE ibm.std_ulogic_function_support.ALL;
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library support;
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use support.power_logic_pkg.all;
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------------------------------------------------------------------------
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-- Entity
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------------------------------------------------------------------------
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entity mmq_tlb_lrat_matchline is
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generic (real_addr_width : integer := 42;
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lpid_width : integer := 8;
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lrat_maxsize_log2 : integer := 40; -- 1T largest pgsize
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lrat_minsize_log2 : integer := 20; -- 1M smallest pgsize
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have_xbit : integer := 1;
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num_pgsizes : integer := 8;
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have_cmpmask : integer := 1;
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cmpmask_width : integer := 7);
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port( -- @{default:nclk}@
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vdd : inout power_logic;
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gnd : inout power_logic;
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addr_in : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1);
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addr_enable : in std_ulogic;
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entry_size : in std_ulogic_vector(0 to 3);
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entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1);
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entry_xbit : in std_ulogic;
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entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1);
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entry_lpn : in std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2-1);
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entry_lpid : in std_ulogic_vector(0 to lpid_width-1);
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comp_lpid : in std_ulogic_vector(0 to lpid_width-1);
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lpid_enable : in std_ulogic;
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entry_v : in std_ulogic;
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match : out std_ulogic;
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dbg_addr_match : out std_ulogic;
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dbg_lpid_match : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end mmq_tlb_lrat_matchline;
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architecture mmq_tlb_lrat_matchline of mmq_tlb_lrat_matchline is
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------------------------------------------------------------------------
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-- Signals
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------------------------------------------------------------------------
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signal entry_lpn_b : std_ulogic_vector(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1);
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signal function_24_43 : std_ulogic;
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signal function_26_43 : std_ulogic;
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signal function_30_43 : std_ulogic;
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signal function_32_43 : std_ulogic;
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signal function_34_43 : std_ulogic;
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signal function_36_43 : std_ulogic;
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signal function_40_43 : std_ulogic;
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signal pgsize_eq_16M : std_ulogic; -- PS7
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signal pgsize_eq_256M : std_ulogic; -- PS9
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signal pgsize_eq_1G : std_ulogic; -- PS10
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signal pgsize_eq_4G : std_ulogic; -- PS11
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signal pgsize_eq_16G : std_ulogic; -- PS12
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signal pgsize_eq_256G : std_ulogic; -- PS14
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signal pgsize_eq_1T : std_ulogic; -- PS15
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signal pgsize_gte_16M : std_ulogic; -- PS7
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signal pgsize_gte_256M : std_ulogic; -- PS9
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signal pgsize_gte_1G : std_ulogic; -- PS10
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signal pgsize_gte_4G : std_ulogic; -- PS11
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signal pgsize_gte_16G : std_ulogic; -- PS12
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signal pgsize_gte_256G : std_ulogic; -- PS14
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signal pgsize_gte_1T : std_ulogic; -- PS15
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signal comp_or_24_25 : std_ulogic;
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signal comp_or_26_29 : std_ulogic;
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signal comp_or_30_31 : std_ulogic;
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signal comp_or_32_33 : std_ulogic;
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signal comp_or_34_35 : std_ulogic;
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signal comp_or_36_39 : std_ulogic;
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signal comp_or_40_43 : std_ulogic;
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signal match_line : std_ulogic_vector(64-real_addr_width to 64-lrat_minsize_log2+lpid_width-1);
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signal addr_match : std_ulogic;
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signal lpid_match : std_ulogic;
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signal unused_dc : std_ulogic;
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-- synopsys translate_off
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-- synopsys translate_on
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begin
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match_line(64-real_addr_width to 64-lrat_minsize_log2+lpid_width-1) <= not(
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(entry_lpn(64-real_addr_width to 64-lrat_minsize_log2-1) & entry_lpid(0 to lpid_width-1)) xor
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(addr_in(64-real_addr_width to 64-lrat_minsize_log2-1) & comp_lpid(0 to lpid_width-1))
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);
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numpgsz8 : if num_pgsizes = 8 generate
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entry_lpn_b(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1) <= not(entry_lpn(64-lrat_maxsize_log2 to 64-lrat_minsize_log2-1));
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gen_nocmpmask80 : if have_cmpmask = 0 generate
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pgsize_eq_16M <= '1' when (entry_size="0111") -- PS7
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else '0';
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pgsize_eq_256M <= '1' when (entry_size="1001") -- PS9
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else '0';
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pgsize_eq_1G <= '1' when (entry_size="1010") -- PS10
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else '0';
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pgsize_eq_4G <= '1' when (entry_size="1011") -- PS11
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else '0';
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pgsize_eq_16G <= '1' when (entry_size="1100") -- PS12
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else '0';
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pgsize_eq_256G <= '1' when (entry_size="1110") -- PS14
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else '0';
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pgsize_eq_1T <= '1' when (entry_size="1111") -- PS15
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else '0';
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pgsize_gte_16M <= '1' when (entry_size="0111" or -- PS7 or larger
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pgsize_gte_256M='1')
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else '0';
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pgsize_gte_256M <= '1' when (entry_size="1001" or -- PS9 or larger
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pgsize_gte_1G='1')
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else '0';
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pgsize_gte_1G <= '1' when (entry_size="1010" or -- PS10 or larger
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pgsize_gte_4G='1')
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else '0';
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pgsize_gte_4G <= '1' when (entry_size="1011" or -- PS11 or larger
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pgsize_gte_16G='1')
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else '0';
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pgsize_gte_16G <= '1' when (entry_size="1100" or -- PS12 or larger
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pgsize_gte_256G='1')
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else '0';
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pgsize_gte_256G <= '1' when (entry_size="1110" or -- PS14 or larger
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pgsize_gte_1T='1')
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else '0';
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pgsize_gte_1T <= '1' when (entry_size="1111") -- PS15
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else '0';
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end generate gen_nocmpmask80;
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gen_cmpmask80 : if have_cmpmask = 1 generate
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-- size entry_cmpmask: 0123456
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-- 1TB 1111111
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-- 256GB 0111111
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-- 16GB 0011111
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-- 4GB 0001111
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-- 1GB 0000111
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-- 256MB 0000011
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-- 16MB 0000001
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-- 1MB 0000000
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pgsize_gte_1T <= entry_cmpmask(0);
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pgsize_gte_256G <= entry_cmpmask(1);
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pgsize_gte_16G <= entry_cmpmask(2);
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pgsize_gte_4G <= entry_cmpmask(3);
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pgsize_gte_1G <= entry_cmpmask(4);
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pgsize_gte_256M <= entry_cmpmask(5);
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pgsize_gte_16M <= entry_cmpmask(6);
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-- size entry_xbitmask: 0123456
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-- 1TB 1000000
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-- 256GB 0100000
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-- 16GB 0010000
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-- 4GB 0001000
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-- 1GB 0000100
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-- 256MB 0000010
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-- 16MB 0000001
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-- 1MB 0000000
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pgsize_eq_1T <= entry_xbitmask(0);
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pgsize_eq_256G <= entry_xbitmask(1);
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pgsize_eq_16G <= entry_xbitmask(2);
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pgsize_eq_4G <= entry_xbitmask(3);
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pgsize_eq_1G <= entry_xbitmask(4);
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pgsize_eq_256M <= entry_xbitmask(5);
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pgsize_eq_16M <= entry_xbitmask(6);
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end generate gen_cmpmask80;
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gen_noxbit80 : if have_xbit = 0 generate
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function_24_43 <= '0';
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function_26_43 <= '0';
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function_30_43 <= '0';
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function_32_43 <= '0';
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function_34_43 <= '0';
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function_36_43 <= '0';
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function_40_43 <= '0';
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end generate gen_noxbit80;
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gen_xbit80 : if (have_xbit /= 0 and real_addr_width=42) generate
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function_24_43 <= not(entry_xbit) or
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not(pgsize_eq_1T) or
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or_reduce(entry_lpn_b(24 to 43) and addr_in(24 to 43));
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function_26_43 <= not(entry_xbit) or
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not(pgsize_eq_256G) or
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or_reduce(entry_lpn_b(26 to 43) and addr_in(26 to 43));
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function_30_43 <= not(entry_xbit) or
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not(pgsize_eq_16G) or
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or_reduce(entry_lpn_b(30 to 43) and addr_in(30 to 43));
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function_32_43 <= not(entry_xbit) or
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not(pgsize_eq_4G) or
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or_reduce(entry_lpn_b(32 to 43) and addr_in(32 to 43));
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function_34_43 <= not(entry_xbit) or
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not(pgsize_eq_1G) or
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or_reduce(entry_lpn_b(34 to 43) and addr_in(34 to 43));
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function_36_43 <= not(entry_xbit) or
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not(pgsize_eq_256M) or
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or_reduce(entry_lpn_b(36 to 43) and addr_in(36 to 43));
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function_40_43 <= not(entry_xbit) or
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not(pgsize_eq_16M) or
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or_reduce(entry_lpn_b(40 to 43) and addr_in(40 to 43));
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end generate gen_xbit80;
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gen_xbit81 : if (have_xbit /= 0 and real_addr_width=32) generate
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function_24_43 <= '1';
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function_26_43 <= '1';
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function_30_43 <= '1';
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function_32_43 <= '1';
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function_34_43 <= not(entry_xbit) or
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not(pgsize_eq_1G) or
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or_reduce(entry_lpn_b(34 to 43) and addr_in(34 to 43));
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function_36_43 <= not(entry_xbit) or
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not(pgsize_eq_256M) or
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or_reduce(entry_lpn_b(36 to 43) and addr_in(36 to 43));
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function_40_43 <= not(entry_xbit) or
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not(pgsize_eq_16M) or
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or_reduce(entry_lpn_b(40 to 43) and addr_in(40 to 43));
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end generate gen_xbit81;
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gen_comp80 : if real_addr_width=42 generate
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comp_or_24_25 <= and_reduce(match_line(24 to 25)) or pgsize_gte_1T;
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comp_or_26_29 <= and_reduce(match_line(26 to 29)) or pgsize_gte_256G;
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comp_or_30_31 <= and_reduce(match_line(30 to 31)) or pgsize_gte_16G;
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comp_or_32_33 <= and_reduce(match_line(32 to 33)) or pgsize_gte_4G;
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comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G;
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comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M;
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comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
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end generate gen_comp80;
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gen_comp81 : if real_addr_width=32 generate
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comp_or_24_25 <= '1';
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comp_or_26_29 <= '1';
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comp_or_30_31 <= '1';
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comp_or_32_33 <= '1';
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comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G;
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comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M;
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comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
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end generate gen_comp81;
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gen_noxbit81 : if (have_xbit = 0 and real_addr_width=42) generate
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addr_match <= ( and_reduce(match_line(22 to 23)) and
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comp_or_24_25 and -- Ignore functions based on page size
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comp_or_26_29 and
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comp_or_30_31 and
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comp_or_32_33 and
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comp_or_34_35 and
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comp_or_36_39 and
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comp_or_40_43 ) or -- Regular compare largest page size
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not(addr_enable); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_noxbit81;
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gen_noxbit82 : if (have_xbit = 0 and real_addr_width=32) generate
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addr_match <= ( and_reduce(match_line(32 to 33)) and
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comp_or_34_35 and -- Ignore functions based on page size
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comp_or_36_39 and
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comp_or_40_43 ) or -- Regular compare largest page size
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not(addr_enable); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_noxbit82;
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gen_xbit82 : if (have_xbit /= 0 and real_addr_width=42) generate
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addr_match <= (and_reduce(match_line(22 to 23)) and
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comp_or_24_25 and -- Ignore functions based on page size
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comp_or_26_29 and
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comp_or_30_31 and
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comp_or_32_33 and
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comp_or_34_35 and
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comp_or_36_39 and
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comp_or_40_43 and
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function_24_43 and -- Exclusion functions
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function_26_43 and
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function_30_43 and
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function_32_43 and
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function_34_43 and
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function_36_43 and
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function_40_43) or -- Regular compare largest page size
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not(addr_enable); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_xbit82;
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gen_xbit83 : if (have_xbit /= 0 and real_addr_width=32) generate
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addr_match <= (and_reduce(match_line(32 to 33)) and
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comp_or_34_35 and -- Ignore functions based on page size
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comp_or_36_39 and
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comp_or_40_43 and
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function_34_43 and -- Exclusion functions
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function_36_43 and
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function_40_43) or -- Regular compare largest page size
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not(addr_enable); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_xbit83;
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end generate numpgsz8; -- numpgsz8: num_pgsizes = 8
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-- entry_lpid=0 ignores lpid match for translation, not invalidation
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lpid_match <= and_reduce(match_line(64-lrat_minsize_log2 to 64-lrat_minsize_log2+lpid_width-1)) or
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not(or_reduce(entry_lpid(0 to 7))) or
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not(lpid_enable);
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match <= addr_match and -- Address compare
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lpid_match and -- LPID compare
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entry_v; -- Valid
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-- debug outputs
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dbg_addr_match <= addr_match; -- out std_ulogic;
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dbg_lpid_match <= lpid_match; -- out std_ulogic;
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gen_unused0 : if have_cmpmask = 0 generate
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unused_dc <= '0';
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end generate gen_unused0;
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gen_unused1 : if have_cmpmask = 1 generate
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unused_dc <= or_reduce(entry_size);
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end generate gen_unused1;
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end mmq_tlb_lrat_matchline;
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