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212 lines
6.9 KiB
VHDL
212 lines
6.9 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--
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-- Description: Pervasive ABIST bolt-on sync and staging
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--
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity pcq_abist_bolton_stg is
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generic(expand_type : integer := 2); -- 0=ibm (umbra), 1=non-ibm, 2=ibm (mpg)
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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pc_pc_ccflush_dc : in std_ulogic;
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pu_pc_bo_enable : in std_ulogic;
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pu_pc_bo_go : in std_ulogic;
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pu_pc_bo_cntlclk : in std_ulogic;
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pu_pc_bo_reset : in std_ulogic;
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pu_pc_bo_fcshdata : in std_ulogic;
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pu_pc_bo_fcreset : in std_ulogic;
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pc_bx_bo_enable_3 : out std_ulogic;
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pc_fu_bo_enable_3 : out std_ulogic;
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pc_iu_bo_enable_4 : out std_ulogic;
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pc_mm_bo_enable_4 : out std_ulogic;
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pc_xu_bo_enable_3 : out std_ulogic;
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pc_pc_bo_go_0 : out std_ulogic;
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pc_pc_bo_enable_0 : out std_ulogic;
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pc_pc_bo_cntlclk_0 : out std_ulogic;
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pc_pc_bo_reset_0 : out std_ulogic;
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pc_pc_bo_fcshdata_0 : out std_ulogic;
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pc_pc_bo_fcreset_0 : out std_ulogic);
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-- synopsys translate_off
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-- synopsys translate_on
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end pcq_abist_bolton_stg;
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architecture pcq_abist_bolton_stg of pcq_abist_bolton_stg is
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signal pc_all_bolton_enable_5 : std_ulogic;
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signal pc_all_bolton_enable_4 : std_ulogic;
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signal pc_all_bolton_enable_3_int : std_ulogic;
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signal pc_pc_bolton_enable_2 : std_ulogic;
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signal pc_pc_bolton_enable_1 : std_ulogic;
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signal pc_pc_bolton_go_1 : std_ulogic;
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signal pc_pc_bc_cntlclk_1 : std_ulogic;
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signal pc_pc_bc_reset_1 : std_ulogic;
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signal pc_pc_bc_fcshdata_1 : std_ulogic;
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signal pc_pc_bc_fcreset_1 : std_ulogic;
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begin
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bolton_enable_sync_meta : entity tri.tri_plat -- non-scan plats, cannot use tri_async_lt scan latch for this
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generic map(
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width => 6,
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expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pu_pc_bo_enable,
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din(1) => pu_pc_bo_go,
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din(2) => pu_pc_bo_cntlclk,
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din(3) => pu_pc_bo_reset,
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din(4) => pu_pc_bo_fcshdata,
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din(5) => pu_pc_bo_fcreset,
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q(0) => pc_all_bolton_enable_5,
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q(1) => pc_pc_bolton_go_1,
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q(2) => pc_pc_bc_cntlclk_1,
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q(3) => pc_pc_bc_reset_1,
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q(4) => pc_pc_bc_fcshdata_1,
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q(5) => pc_pc_bc_fcreset_1);
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bolton_enable_sync : entity tri.tri_plat -- non-scan plats, cannot use tri_async_lt scan latch for this
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generic map(
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width => 6,
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expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pc_all_bolton_enable_5,
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din(1) => pc_pc_bolton_go_1,
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din(2) => pc_pc_bc_cntlclk_1,
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din(3) => pc_pc_bc_reset_1,
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din(4) => pc_pc_bc_fcshdata_1,
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din(5) => pc_pc_bc_fcreset_1,
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q(0) => pc_all_bolton_enable_4,
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q(1) => pc_pc_bo_go_0,
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q(2) => pc_pc_bo_cntlclk_0,
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q(3) => pc_pc_bo_reset_0,
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q(4) => pc_pc_bo_fcshdata_0,
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q(5) => pc_pc_bo_fcreset_0);
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bolton_enable_sync_2 : entity tri.tri_plat -- non-scan plats, cannot use tri_async_lt scan latch for this
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generic map(
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width => 4,
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expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pc_all_bolton_enable_4,
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din(1) => pc_all_bolton_enable_3_int,
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din(2) => pc_pc_bolton_enable_2,
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din(3) => pc_pc_bolton_enable_1,
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q(0) => pc_all_bolton_enable_3_int,
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q(1) => pc_pc_bolton_enable_2,
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q(2) => pc_pc_bolton_enable_1,
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q(3) => pc_pc_bo_enable_0);
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-- Splitting out bx/fu/xu unit bolton_enable signals 4to3 staging for placement + timing
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bx_bolton_enable_4_3 : entity tri.tri_plat
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generic map( width => 1, expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pc_all_bolton_enable_4,
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q(0) => pc_bx_bo_enable_3 );
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fu_bolton_enable_4_3 : entity tri.tri_plat
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generic map( width => 1, expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pc_all_bolton_enable_4,
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q(0) => pc_fu_bo_enable_3 );
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xu_bolton_enable_4_3 : entity tri.tri_plat
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generic map( width => 1, expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pc_all_bolton_enable_4,
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q(0) => pc_xu_bo_enable_3 );
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-- Splitting out iu/mm unit bolton_enable signals 5to4 staging for placement + timing
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iu_bolton_enable_5_4 : entity tri.tri_plat
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generic map( width => 1, expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pc_all_bolton_enable_5,
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q(0) => pc_iu_bo_enable_4 );
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mm_bolton_enable_5_4 : entity tri.tri_plat
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generic map( width => 1, expand_type => expand_type)
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port map(
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_pc_ccflush_dc,
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din(0) => pc_all_bolton_enable_5,
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q(0) => pc_mm_bo_enable_4 );
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end architecture pcq_abist_bolton_stg;
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