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294 lines
12 KiB
VHDL
294 lines
12 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--
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-- Description: Pervasive Core LCB Control Component
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--
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity pcq_clks_ctrl is
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generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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);
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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rtim_sl_thold_5 : in std_ulogic;
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func_sl_thold_5 : in std_ulogic;
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func_nsl_thold_5 : in std_ulogic;
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ary_nsl_thold_5 : in std_ulogic;
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sg_5 : in std_ulogic;
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fce_5 : in std_ulogic;
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gsd_test_enable_dc : in std_ulogic;
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gsd_test_acmode_dc : in std_ulogic;
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ccflush_dc : in std_ulogic;
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ccenable_dc : in std_ulogic;
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scan_type_dc : in std_ulogic_vector(0 to 8);
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lbist_en_dc : in std_ulogic;
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lbist_ip_dc : in std_ulogic;
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rg_ck_fast_xstop : in std_ulogic;
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ct_ck_pm_ccflush_disable : in std_ulogic;
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ct_ck_pm_raise_tholds : in std_ulogic;
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-- --Thold + control outputs to the units
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pc_pc_ccflush_out_dc : out std_ulogic;
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pc_pc_gptr_sl_thold_4 : out std_ulogic;
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pc_pc_time_sl_thold_4 : out std_ulogic;
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pc_pc_repr_sl_thold_4 : out std_ulogic;
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pc_pc_cfg_sl_thold_4 : out std_ulogic;
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pc_pc_cfg_slp_sl_thold_4 : out std_ulogic;
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pc_pc_abst_sl_thold_4 : out std_ulogic;
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pc_pc_abst_slp_sl_thold_4 : out std_ulogic;
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pc_pc_regf_sl_thold_4 : out std_ulogic;
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pc_pc_regf_slp_sl_thold_4 : out std_ulogic;
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pc_pc_func_sl_thold_4 : out std_ulogic_vector(0 to 1);
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pc_pc_func_slp_sl_thold_4 : out std_ulogic_vector(0 to 1);
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pc_pc_func_nsl_thold_4 : out std_ulogic;
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pc_pc_func_slp_nsl_thold_4 : out std_ulogic;
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pc_pc_ary_nsl_thold_4 : out std_ulogic;
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pc_pc_ary_slp_nsl_thold_4 : out std_ulogic;
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pc_pc_rtim_sl_thold_4 : out std_ulogic;
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pc_pc_sg_4 : out std_ulogic_vector(0 to 1);
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pc_pc_fce_4 : out std_ulogic_vector(0 to 1)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end pcq_clks_ctrl;
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architecture pcq_clks_ctrl of pcq_clks_ctrl is
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-- Scan ring select decodes for scan_type_dc vector
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constant scantype_func : natural := 0;
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constant scantype_mode : natural := 1;
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constant scantype_ccfg : natural := 2;
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constant scantype_gptr : natural := 2;
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constant scantype_regf : natural := 3;
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constant scantype_fuse : natural := 3;
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constant scantype_lbst : natural := 4;
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constant scantype_abst : natural := 5;
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constant scantype_repr : natural := 6;
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constant scantype_time : natural := 7;
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constant scantype_bndy : natural := 8;
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constant scantype_fary : natural := 9;
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signal scan_type_b : std_ulogic_vector(0 to 8); -- scantype;
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signal fast_xstop_gated_staged : std_ulogic;
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signal fce_in, sg_in : std_ulogic;
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signal ary_nsl_thold, func_nsl_thold : std_ulogic;
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signal rtim_sl_thold, func_sl_thold : std_ulogic;
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signal gptr_sl_thold_in : std_ulogic;
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signal time_sl_thold_in : std_ulogic;
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signal repr_sl_thold_in : std_ulogic;
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signal rtim_sl_thold_in : std_ulogic;
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signal cfg_run_sl_thold_in : std_ulogic;
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signal cfg_slp_sl_thold_in : std_ulogic;
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signal abst_run_sl_thold_in : std_ulogic;
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signal abst_slp_sl_thold_in : std_ulogic;
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signal regf_run_sl_thold_in : std_ulogic;
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signal regf_slp_sl_thold_in : std_ulogic;
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signal func_run_sl_thold_in : std_ulogic;
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signal func_slp_sl_thold_in : std_ulogic;
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signal func_run_nsl_thold_in : std_ulogic;
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signal func_slp_nsl_thold_in : std_ulogic;
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signal ary_run_nsl_thold_in : std_ulogic;
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signal ary_slp_nsl_thold_in : std_ulogic;
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signal pm_ccflush_disable_dc : std_ulogic;
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signal ccflush_out_dc_int : std_ulogic;
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signal testdc : std_ulogic;
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signal thold_overide_ctrl : std_ulogic;
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signal unused_signals : std_ulogic;
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begin
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-- unused signals
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unused_signals <= or_reduce(scan_type_b(2) & scan_type_b(4) & scan_type_b(6 to 8) & lbist_ip_dc);
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-- detect test dc mode
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testdc <= gsd_test_enable_dc and not gsd_test_acmode_dc;
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-- enable sg/fce before latching
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sg_in <= sg_5 and ccenable_dc;
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fce_in <= fce_5 and ccenable_dc;
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-- scan chain type
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scan_type_b <= GATE_AND(sg_in, not scan_type_dc);
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-- setup for xx_thold_5 inputs
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thold_overide_ctrl <= fast_xstop_gated_staged and not sg_in and not lbist_en_dc and not gsd_test_enable_dc;
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rtim_sl_thold <= rtim_sl_thold_5;
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func_sl_thold <= func_sl_thold_5 OR thold_overide_ctrl;
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func_nsl_thold <= func_nsl_thold_5 OR thold_overide_ctrl;
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ary_nsl_thold <= ary_nsl_thold_5 OR thold_overide_ctrl;
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-- setup for plat flush control signals
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-- Active when power_management enabled (PM_Sleep_enable or PM_RVW_enable active)
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-- If plats were in flush mode, forces plats to be clocked again for power-savings.
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pm_ccflush_disable_dc <= ct_ck_pm_ccflush_disable;
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ccflush_out_dc_int <= ccflush_dc AND (NOT pm_ccflush_disable_dc OR lbist_en_dc OR testdc);
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pc_pc_ccflush_out_dc <= ccflush_out_dc_int;
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-- OR and MUX of thold signals
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-- scan only: stop if not scanning, not part of LBIST, hence no sg_in here
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gptr_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_gptr) or not ccenable_dc;
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-- scan only: stop if not scanning, not part of LBIST, hence no sg_in here
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time_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_time) or not ccenable_dc;
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-- scan only: stop if not scanning, not part of LBIST, hence no sg_in here
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repr_sl_thold_in <= func_sl_thold or not scan_type_dc(scantype_repr) or not ccenable_dc;
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cfg_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_mode) or
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(ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc);
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cfg_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_mode);
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abst_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_abst) or
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(ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc);
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abst_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_abst);
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regf_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_regf) or
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(ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc);
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regf_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_regf);
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func_run_sl_thold_in <= func_sl_thold or scan_type_b(scantype_func) or
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(ct_ck_pm_raise_tholds and not sg_in and not lbist_en_dc and not gsd_test_enable_dc);
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func_slp_sl_thold_in <= func_sl_thold or scan_type_b(scantype_func);
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func_run_nsl_thold_in <= func_nsl_thold or
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(ct_ck_pm_raise_tholds and not fce_in and not lbist_en_dc and not gsd_test_enable_dc);
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func_slp_nsl_thold_in <= func_nsl_thold;
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ary_run_nsl_thold_in <= ary_nsl_thold or
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(ct_ck_pm_raise_tholds and not fce_in and not lbist_en_dc and not gsd_test_enable_dc);
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ary_slp_nsl_thold_in <= ary_nsl_thold;
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rtim_sl_thold_in <= rtim_sl_thold;
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-- PLAT staging/redrive
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fast_stop_staging: tri_plat
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generic map( width => 1, expand_type => expand_type)
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port map( vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => ccflush_out_dc_int,
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din(0) => rg_ck_fast_xstop,
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q(0) => fast_xstop_gated_staged
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);
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sg_fce_plat: tri_plat
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generic map(width => 4, expand_type => expand_type)
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port map( vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => ccflush_out_dc_int,
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din(0) => sg_in,
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din(1) => sg_in,
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din(2) => fce_in,
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din(3) => fce_in,
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q(0) => pc_pc_sg_4(0),
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q(1) => pc_pc_sg_4(1),
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q(2) => pc_pc_fce_4(0),
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q(3) => pc_pc_fce_4(1)
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);
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thold_plat: tri_plat
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generic map( width => 18, expand_type => expand_type)
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port map( vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => ccflush_out_dc_int,
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din( 0) => gptr_sl_thold_in,
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din( 1) => time_sl_thold_in,
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din( 2) => repr_sl_thold_in,
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din( 3) => cfg_run_sl_thold_in,
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din( 4) => cfg_slp_sl_thold_in,
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din( 5) => abst_run_sl_thold_in,
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din( 6) => abst_slp_sl_thold_in,
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din( 7) => regf_run_sl_thold_in,
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din( 8) => regf_slp_sl_thold_in,
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din( 9) => func_run_sl_thold_in,
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din(10) => func_run_sl_thold_in,
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din(11) => func_slp_sl_thold_in,
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din(12) => func_slp_sl_thold_in,
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din(13) => func_run_nsl_thold_in,
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din(14) => func_slp_nsl_thold_in,
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din(15) => ary_run_nsl_thold_in,
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din(16) => ary_slp_nsl_thold_in,
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din(17) => rtim_sl_thold_in,
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q( 0) => pc_pc_gptr_sl_thold_4,
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q( 1) => pc_pc_time_sl_thold_4,
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q( 2) => pc_pc_repr_sl_thold_4,
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q( 3) => pc_pc_cfg_sl_thold_4,
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q( 4) => pc_pc_cfg_slp_sl_thold_4,
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q( 5) => pc_pc_abst_sl_thold_4,
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q( 6) => pc_pc_abst_slp_sl_thold_4,
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q( 7) => pc_pc_regf_sl_thold_4,
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q( 8) => pc_pc_regf_slp_sl_thold_4,
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q( 9) => pc_pc_func_sl_thold_4(0),
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q(10) => pc_pc_func_sl_thold_4(1),
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q(11) => pc_pc_func_slp_sl_thold_4(0),
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q(12) => pc_pc_func_slp_sl_thold_4(1),
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q(13) => pc_pc_func_nsl_thold_4,
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q(14) => pc_pc_func_slp_nsl_thold_4,
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q(15) => pc_pc_ary_nsl_thold_4,
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q(16) => pc_pc_ary_slp_nsl_thold_4,
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q(17) => pc_pc_rtim_sl_thold_4
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);
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end pcq_clks_ctrl;
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