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453 lines
20 KiB
VHDL
453 lines
20 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--
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-- Description: Pervasive Core Thread Controls
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--
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity pcq_ctrl is
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generic(expand_type : integer := 2 -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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);
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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scan_dis_dc_b : in std_ulogic;
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lcb_clkoff_dc_b : in std_ulogic;
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lcb_mpw1_dc_b : in std_ulogic;
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lcb_mpw2_dc_b : in std_ulogic;
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lcb_delay_lclkr_dc : in std_ulogic;
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lcb_act_dis_dc : in std_ulogic;
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pc_pc_func_slp_sl_thold_0 : in std_ulogic;
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pc_pc_sg_0 : in std_ulogic;
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func_scan_in : in std_ulogic;
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func_scan_out : out std_ulogic;
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-- Reset Related
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an_ac_reset_1_complete : in std_ulogic;
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an_ac_reset_2_complete : in std_ulogic;
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an_ac_reset_3_complete : in std_ulogic;
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an_ac_reset_wd_complete : in std_ulogic;
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pc_xu_reset_1_cmplt : out std_ulogic;
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pc_xu_reset_2_cmplt : out std_ulogic;
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pc_xu_reset_3_cmplt : out std_ulogic;
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pc_xu_reset_wd_cmplt : out std_ulogic;
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pc_xu_init_reset : out std_ulogic;
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pc_iu_init_reset : out std_ulogic;
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ct_rg_hold_during_init : out std_ulogic;
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-- Power Management
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ct_rg_power_managed : out std_ulogic_vector(0 to 3);
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ct_rg_pm_thread_stop : out std_ulogic_vector(0 to 3);
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an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3);
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ac_an_power_managed : out std_ulogic;
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ac_an_rvwinkle_mode : out std_ulogic;
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ct_ck_pm_ccflush_disable : out std_ulogic;
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ct_ck_pm_raise_tholds : out std_ulogic;
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rg_ct_dis_pwr_savings : in std_ulogic;
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xu_pc_spr_ccr0_pme : in std_ulogic_vector(0 to 1);
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xu_pc_spr_ccr0_we : in std_ulogic_vector(0 to 3);
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-- Trace/Trigger Signals
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dbg_ctrls : out std_ulogic_vector(0 to 36)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end pcq_ctrl;
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architecture pcq_ctrl of pcq_ctrl is
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--=====================================================================
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-- Signal Declarations
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--=====================================================================
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constant initactive_size : positive := 1;
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constant resetsm_size : positive := 5;
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constant initerat_size : positive := 1;
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constant pmstate_size : positive := 14;
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constant sprccr0_size : positive := 6;
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constant pmstop_size : positive := 4;
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constant resetstat_size : positive := 4;
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constant sparectrl_size : positive := 6;
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-----------------------------------------------------------------------
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-- Scan Ring Ordering:
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-- start of func scan chain ordering
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constant initactive_offset : natural := 0;
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constant resetsm_offset : natural := initactive_offset + initactive_size;
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constant initerat_offset : natural := resetsm_offset + resetsm_size;
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constant pmstate_offset : natural := initerat_offset + initerat_size;
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constant sprccr0_offset : natural := pmstate_offset + pmstate_size;
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constant pmstop_offset : natural := sprccr0_offset + sprccr0_size;
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constant resetstat_offset : natural := pmstop_offset + pmstop_size;
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constant sparectrl_offset : natural := resetstat_offset + resetstat_size;
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constant func_right : natural := sparectrl_offset + sparectrl_size - 1;
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-- end of func scan chain ordering
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-----------------------------------------------------------------------
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-- Reset State Machine:
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constant ResSM_Idle : std_ulogic_vector(0 to 4) := "00000";
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constant ResSM_Start : std_ulogic_vector(0 to 4) := "00001";
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constant ResSM_InitErat : std_ulogic_vector(0 to 4) := "00111";
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constant ResSM_Return : std_ulogic_vector(0 to 4) := "10111";
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-----------------------------------------------------------------------
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-- Basic/Misc signals
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signal tiup : std_ulogic;
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signal func_siv, func_sov : std_ulogic_vector(0 to func_right);
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signal pc_pc_func_slp_sl_thold_0_b : std_ulogic;
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signal force_funcslp : std_ulogic;
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-- Reset Signals
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signal resetsm_active : std_ulogic;
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signal resetsm_act_ctrl : std_ulogic;
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-- Power management Signals
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signal spr_ccr0_pme_q : std_ulogic_vector(0 to 1);
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signal spr_ccr0_we_q : std_ulogic_vector(0 to 3);
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signal pm_sleep_enable : std_ulogic;
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signal pm_rvw_enable : std_ulogic;
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signal thread_stopped : std_ulogic_vector(0 to 3);
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-- Latch definitions begin
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signal resetsm_d, resetsm_q : std_ulogic_vector(0 to resetsm_size-1);
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signal init_active_d, init_active_q : std_ulogic;
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signal initerat_d, initerat_q : std_ulogic;
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signal pmstate_d, pmstate_q : std_ulogic_vector(0 to 3);
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signal pmstate_all_d, pmstate_all_q : std_ulogic;
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signal pmclkctrl_dly_d, pmclkctrl_dly_q : std_ulogic_vector(0 to 7);
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signal rvwinkled_d, rvwinkled_q : std_ulogic;
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signal pmstop_q : std_ulogic_vector(0 to pmstop_size-1);
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signal reset_complete_q : std_ulogic_vector(0 to resetstat_size-1);
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signal pm_ccflush_disable_int : std_ulogic;
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signal pm_raise_tholds_int : std_ulogic;
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signal spare_ctrl_wrapped_q : std_ulogic_vector(0 to sparectrl_size-1);
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begin
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tiup <= '1';
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--=====================================================================
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-- Reset State Machine
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--=====================================================================
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-- Counter used to generate reset control pulses.
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-- Starts when clocks start because init_active_q inits to 1.
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-- Keeps counting until init_active_q is reset, then returns to Idle state.
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resetsm_d <= (others=>'0') when (resetsm_q=ResSM_Idle and init_active_q='0') else
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ResSM_Start when (resetsm_q=ResSM_Idle and init_active_q='1') else
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ResSM_Idle when init_active_q='0' else
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resetsm_q + "00001";
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resetsm_active <= or_reduce(resetsm_q);
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resetsm_act_ctrl <= init_active_q or resetsm_active;
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-- The initerat latch controls the init_reset signals to IU and XU.
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-- Goes active when ResSM=8. Goes inactive 16 clock cycles later when ResSM returns to Idle.
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initerat_d <= '0' when resetsm_q=ResSM_Idle else
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'0' when resetsm_q=ResSM_Return else
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'1' when resetsm_q=ResSM_InitErat else
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initerat_q;
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-- init_active_q initializes to '1'; cleared when Reset_SM count completes (ResSM >= 24).
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init_active_d <= '0' when resetsm_q(0 to 1)="11" else init_active_q;
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--=====================================================================
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-- Power Management Latches
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--=====================================================================
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-- XU signals indicate when power-savings is enabled (sleep or rvw modes), and which
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-- threads are stopped.
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-- The pmstate latch tracks which threads are stopped when either power-savings mode
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-- is enabled. The rvwinkled latch only when pm_rvw_enable is set.
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-- If all threads are stopped when power-savings is enabled, then signals to the
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-- clock control macro will initiate power savings actions. These controls force
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-- ccflush_dc inactive to ensure all PLATs are clocking. After a delay period, the
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-- run tholds will be raised to stop clocks.
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-- When coming out of power-savings, the tholds will be disabled prior to deactivating
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-- ccflush_dc.
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pm_sleep_enable <= not spr_ccr0_pme_q(0) and spr_ccr0_pme_q(1);
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pm_rvw_enable <= spr_ccr0_pme_q(0) and not spr_ccr0_pme_q(1);
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thread_stopped <= spr_ccr0_we_q;
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pmstate_d <= gate_and((pm_sleep_enable or pm_rvw_enable) and not resetsm_active,
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thread_stopped(0 to 3));
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pmstate_all_d <= and_reduce(pmstate_q);
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pmclkctrl_dly_d(0 to 7) <= pmstate_all_q & pmclkctrl_dly_q(0 to 6);
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rvwinkled_d <= pmclkctrl_dly_q(6) and pm_rvw_enable;
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--=====================================================================
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-- Outputs
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--=====================================================================
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-- Used as part of thread stop signal to XU.
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-- Keeps threads stopped until after the Reset SM completes count.
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ct_rg_hold_during_init <= init_active_q;
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-- Init pulse to IU and XU to force initialization of I/D-ERATs.
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-- IU also holds instruction fetch until init signal released.
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pc_iu_init_reset <= initerat_q;
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pc_xu_init_reset <= initerat_q;
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-- Software initiated reset status to XU for DBSR[MRR] and TSR[WRS]
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pc_xu_reset_1_cmplt <= reset_complete_q(0);
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pc_xu_reset_2_cmplt <= reset_complete_q(1);
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pc_xu_reset_3_cmplt <= reset_complete_q(2);
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pc_xu_reset_wd_cmplt <= reset_complete_q(3);
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-- To THRCTL[Tx_PM]; indicates core power-managed due to external input.
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ct_rg_pm_thread_stop <= pmstop_q;
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-- To THRCTL[Tx_PM]; indicates core power-managed via software actions.
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ct_rg_power_managed <= pmstate_q;
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-- Core in rvwinkle power-savings state. L2 can prepare for Chiplet power-down.
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ac_an_rvwinkle_mode <= rvwinkled_q;
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-- Core in power-savings state due to any combination of power-savings instructions
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ac_an_power_managed <= pmclkctrl_dly_q(7);
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-- Goes to clock controls to disable plat flush controls
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pm_ccflush_disable_int <= pmstate_all_q or pmclkctrl_dly_q(7);
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ct_ck_pm_ccflush_disable <= pm_ccflush_disable_int and not rg_ct_dis_pwr_savings;
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-- Goes to clock controls to activate run tholds
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pm_raise_tholds_int <= pmstate_all_q and pmclkctrl_dly_q(7);
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ct_ck_pm_raise_tholds <= pm_raise_tholds_int and not rg_ct_dis_pwr_savings;
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--=====================================================================
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-- Trace/Trigger Signals
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--=====================================================================
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dbg_ctrls <= init_active_q & -- 0
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resetsm_q(0 to 4) & -- 1:5
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initerat_q & -- 6
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reset_complete_q(0 to 3) & -- 7:10
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pmstop_q(0 to 3) & -- 11:14
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pmstate_q(0 to 3) & -- 15:18
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rvwinkled_q & -- 19
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spr_ccr0_pme_q(0 to 1) & -- 20:21
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spr_ccr0_we_q(0 to 3) & -- 22:25
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pmclkctrl_dly_q(0 to 7) & -- 26:33
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rg_ct_dis_pwr_savings & -- 34
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pm_ccflush_disable_int & -- 35
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pm_raise_tholds_int ; -- 36
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--=====================================================================
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-- Latches
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--=====================================================================
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-- func ring registers start
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initactive: tri_rlmlatch_p
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generic map (init => 1, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(initactive_offset),
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scout => func_sov(initactive_offset),
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din => init_active_d,
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dout => init_active_q);
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resetsm: tri_rlmreg_p
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generic map (width => resetsm_size, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => resetsm_act_ctrl,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(resetsm_offset to resetsm_offset + resetsm_size-1),
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scout => func_sov(resetsm_offset to resetsm_offset + resetsm_size-1),
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din => resetsm_d,
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dout => resetsm_q );
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initerat: tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => resetsm_active,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(initerat_offset),
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scout => func_sov(initerat_offset),
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din => initerat_d,
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dout => initerat_q );
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pmstate: tri_rlmreg_p
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generic map (width => pmstate_size, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(pmstate_offset to pmstate_offset + pmstate_size-1),
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scout => func_sov(pmstate_offset to pmstate_offset + pmstate_size-1),
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din(0 to 3) => pmstate_d,
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din(4) => pmstate_all_d,
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din(5) => rvwinkled_d,
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din(6 to 13) => pmclkctrl_dly_d,
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dout(0 to 3) => pmstate_q,
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dout(4) => pmstate_all_q,
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dout(5) => rvwinkled_q,
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dout(6 to 13) => pmclkctrl_dly_q );
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sprccr0: tri_rlmreg_p
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generic map (width => sprccr0_size, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(sprccr0_offset to sprccr0_offset + sprccr0_size-1),
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scout => func_sov(sprccr0_offset to sprccr0_offset + sprccr0_size-1),
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din(0 to 1) => xu_pc_spr_ccr0_pme,
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din(2 to 5) => xu_pc_spr_ccr0_we,
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dout(0 to 1) => spr_ccr0_pme_q,
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dout(2 to 5) => spr_ccr0_we_q );
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pmstop: tri_rlmreg_p
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generic map (width => pmstop_size, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(pmstop_offset to pmstop_offset + pmstop_size-1),
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scout => func_sov(pmstop_offset to pmstop_offset + pmstop_size-1),
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din => an_ac_pm_thread_stop,
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dout => pmstop_q );
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resetstat: tri_rlmreg_p
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generic map (width => resetstat_size, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(resetstat_offset to resetstat_offset + resetstat_size-1),
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scout => func_sov(resetstat_offset to resetstat_offset + resetstat_size-1),
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din(0) => an_ac_reset_1_complete,
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din(1) => an_ac_reset_2_complete,
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din(2) => an_ac_reset_3_complete,
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din(3) => an_ac_reset_wd_complete,
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dout => reset_complete_q );
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sparectrl: tri_rlmreg_p
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generic map (width => sparectrl_size, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_pc_func_slp_sl_thold_0_b,
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sg => pc_pc_sg_0,
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forcee => force_funcslp,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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scin => func_siv(sparectrl_offset to sparectrl_offset + sparectrl_size-1),
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scout => func_sov(sparectrl_offset to sparectrl_offset + sparectrl_size-1),
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din => spare_ctrl_wrapped_q,
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dout => spare_ctrl_wrapped_q );
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-- func ring registers end
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|
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--=====================================================================
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-- Thold/SG Staging
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--=====================================================================
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-- func_slp lcbor
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lcbor_funcslp: tri_lcbor
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generic map (expand_type => expand_type )
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|
port map (
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clkoff_b => lcb_clkoff_dc_b,
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thold => pc_pc_func_slp_sl_thold_0,
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sg => pc_pc_sg_0,
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act_dis => lcb_act_dis_dc,
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forcee => force_funcslp,
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thold_b => pc_pc_func_slp_sl_thold_0_b );
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|
|
|
|
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--=====================================================================
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-- Scan Connections
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--=====================================================================
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-- Func ring
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func_siv(0 TO func_right) <= func_scan_in & func_sov(0 to func_right-1);
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func_scan_out <= func_sov(func_right) and scan_dis_dc_b;
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|
|
|
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-----------------------------------------------------------------------
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end pcq_ctrl;
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