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593 lines
24 KiB
VHDL
593 lines
24 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--
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-- Description: Generic Local FIR Component
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--
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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---------------------------------------------------------------------
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entity pcq_local_fir2 is
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generic(width : positive := 1; -- this must be >=1 and <=64
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expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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impl_lxstop_mchk : boolean := false; -- generate local checkstop /machine check output
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use_recov_reset : boolean := false; -- this adds a reset feature without the second wof register.
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fir_init : std_ulogic_vector := "0"; -- init value for fir register; length = width !
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fir_mask_init : std_ulogic_vector := "0"; -- init value for fir mask register; length = width !
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fir_mask_par_init : std_ulogic_vector := "0"; -- init value for fir mask register even parity
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fir_action0_init : std_ulogic_vector := "0"; -- init value for fir action0 register; length = width !
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fir_action0_par_init : std_ulogic_vector := "0"; -- init value for fir action0 register even parity
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fir_action1_init : std_ulogic_vector := "0"; -- init value for fir action1 register; length = width !
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fir_action1_par_init : std_ulogic_vector := "0"); -- init value for fir action1 register even parity
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port
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-- Global lines for clocking and scan control
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( nclk : in clk_logic
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; vd : inout power_logic
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; gd : inout power_logic
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; lcb_clkoff_dc_b : in std_ulogic --from lcb_cntl external to component
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; lcb_mpw1_dc_b : in std_ulogic --from lcb_cntl external to component
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; lcb_mpw2_dc_b : in std_ulogic --from lcb_cntl external to component
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; lcb_delay_lclkr_dc : in std_ulogic --from lcb_cntl external to component
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; lcb_act_dis_dc : in std_ulogic --from lcb_cntl external to component
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; lcb_sg_0 : in std_ulogic
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; lcb_func_slp_sl_thold_0 : in std_ulogic := '0'
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; lcb_cfg_slp_sl_thold_0 : in std_ulogic := '0'
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; mode_scan_siv : in std_ulogic_vector(0 to 3*(width+1)+width-1) -- scan vector in
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; mode_scan_sov : out std_ulogic_vector(0 to 3*(width+1)+width-1) -- scan vector out
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; func_scan_siv : in std_ulogic_vector(0 to 4)
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; func_scan_sov : out std_ulogic_vector(0 to 4)
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-- External interface
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; sys_xstop_in : in std_ulogic := '0' -- freeze FIR on system checkstop from chip GEM
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; error_in : in std_ulogic_vector(0 to width-1) -- needs to be directly off a latch for timing
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; xstop_err : out std_ulogic -- checkstop output to Global FIR
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; recov_err : out std_ulogic -- recoverable output to Global FIR
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; lxstop_mchk : out std_ulogic -- use ONLY if impl_lxstop_mchk = true
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; trace_error : out std_ulogic -- connect to error_input of closest trdata macro
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; recov_reset : in std_ulogic := '0' -- only needed if use_recov_reset = true
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; fir_out : out std_ulogic_vector(0 to width-1) -- output of current FIR state if needed
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; act0_out : out std_ulogic_vector(0 to width-1) -- output of current FIR Act0 state if needed
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; act1_out : out std_ulogic_vector(0 to width-1) -- output of current FIR Act1 state if needed
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; mask_out : out std_ulogic_vector(0 to width-1) -- output of current FIR Mask state if needed
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; sc_parity_error_inject : in std_ulogic -- Force parity error
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-- SCOM register connections
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; sc_active : in std_ulogic
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; sc_wr_q : in std_ulogic
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; sc_addr_v : in std_ulogic_vector(0 to 8)
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; sc_wdata : in std_ulogic_vector(0 to width-1)
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; sc_wparity : in std_ulogic
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; sc_rdata : out std_ulogic_vector(0 to width-1)
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; fir_parity_check : out std_ulogic_vector(0 to 2) -- Action0, Action1, Mask reg parity checks
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);
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end pcq_local_fir2;
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architecture pcq_local_fir2 of pcq_local_fir2 is
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-- Clocks
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signal func_d1clk : std_ulogic;
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signal func_d2clk : std_ulogic;
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signal func_lclk : clk_logic;
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signal mode_d1clk : std_ulogic;
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signal mode_d2clk : std_ulogic;
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signal mode_lclk : clk_logic;
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signal scom_mode_d1clk : std_ulogic;
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signal scom_mode_d2clk : std_ulogic;
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signal scom_mode_lclk : clk_logic;
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signal func_thold_b : std_ulogic;
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signal func_force : std_ulogic;
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signal mode_thold_b : std_ulogic;
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signal mode_force : std_ulogic;
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-- FIR regs
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signal data_ones : std_ulogic_vector(0 to width-1);
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signal or_fir : std_ulogic_vector(0 to width-1);
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signal and_fir : std_ulogic_vector(0 to width-1);
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signal or_mask : std_ulogic_vector(0 to width-1);
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signal and_mask : std_ulogic_vector(0 to width-1);
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signal fir_mask_in : std_ulogic_vector(0 to width-1);
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signal fir_mask_lt : std_ulogic_vector(0 to width-1);
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signal masked : std_ulogic_vector(0 to width-1);
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signal fir_mask_par_in : std_ulogic;
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signal fir_mask_par_lt : std_ulogic;
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signal fir_mask_par_err : std_ulogic;
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signal fir_action0_in : std_ulogic_vector(0 to width-1);
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signal fir_action0_lt : std_ulogic_vector(0 to width-1);
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signal fir_action0_par_in : std_ulogic;
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signal fir_action0_par_lt : std_ulogic;
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signal fir_action0_par_err : std_ulogic;
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signal fir_action1_in : std_ulogic_vector(0 to width-1);
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signal fir_action1_lt : std_ulogic_vector(0 to width-1);
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signal fir_action1_par_in : std_ulogic;
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signal fir_action1_par_lt : std_ulogic;
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signal fir_action1_par_err : std_ulogic;
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signal fir_reset : std_ulogic_vector(0 to width-1);
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signal error_input : std_ulogic_vector(0 to width-1);
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signal fir_error_in_reef : std_ulogic_vector(0 to width-1);
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signal fir_in : std_ulogic_vector(0 to width-1);
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signal fir_lt : std_ulogic_vector(0 to width-1);
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signal block_fir : std_ulogic;
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signal or_fir_load : std_ulogic;
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signal and_fir_ones : std_ulogic;
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signal and_fir_load : std_ulogic;
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signal or_mask_load : std_ulogic;
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signal and_mask_ones : std_ulogic;
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signal and_mask_load : std_ulogic;
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-- Error report
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signal sys_xstop_lt : std_ulogic;
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signal recov_in : std_ulogic;
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signal recov_lt : std_ulogic;
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signal xstop_in : std_ulogic;
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signal xstop_lt : std_ulogic;
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signal trace_error_in : std_ulogic;
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signal trace_error_lt : std_ulogic;
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-- Other
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signal tieup : std_ulogic;
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-- Scan chain hookups
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signal mode_si, mode_so : std_ulogic_vector(0 to 3*(width+1)+width-1);
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signal func_si, func_so : std_ulogic_vector(0 to 4);
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signal unused_signals : std_ulogic;
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begin
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tieup <= '1';
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data_ones <= (others => '1');
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unused_signals <= or_reduce(recov_reset & sc_addr_v(5));
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--******************************************************
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--* Check width inputs
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--******************************************************
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assert (fir_action0_init'length = width)
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report "fir_action0_init width error, fir_action0_init must be same width as the component instantiation"
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severity error;
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assert (fir_action1_init'length = width)
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report "fir_action1_init width error, fir_action1_init must be same width as the component instantiation"
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severity error;
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assert (fir_mask_init'length = width)
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report "fir_mask_init width error, fir_mask_init must be same width as the component instantiation"
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severity error;
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-- This will cause the compile to fail if the wrong width is entered.
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verify_action0: if (fir_action0_init'length /= width) generate
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fir_in(0 to 95) <= fir_lt(0 to width);
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end generate verify_action0;
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verify_action1: if (fir_action1_init'length /= width) generate
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fir_in(0 to 95) <= fir_lt(0 to width);
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end generate verify_action1;
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verify_action2: if (fir_mask_init'length /= width) generate
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fir_in(0 to 95) <= fir_lt(0 to width);
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end generate verify_action2;
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--******************************************************
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--* LCB driver, LCB and Register Instantiations
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--******************************************************
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-- functional ring regs; NOT power managed
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func_lcbor: entity tri.tri_lcbor
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generic map (expand_type => expand_type )
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port map( clkoff_b => lcb_clkoff_dc_b,
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thold => lcb_func_slp_sl_thold_0,
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sg => lcb_sg_0,
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act_dis => lcb_act_dis_dc,
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forcee => func_force,
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thold_b => func_thold_b
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);
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func_lcb: entity tri.tri_lcbnd
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generic map (expand_type => expand_type )
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port map( act => tieup, -- not power saved
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vd => vd,
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gd => gd,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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nclk => nclk,
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forcee => func_force,
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sg => lcb_sg_0,
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thold_b => func_thold_b,
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d1clk => func_d1clk,
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d2clk => func_d2clk,
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lclk => func_lclk
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);
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-- config ring regs; NOT power managed
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mode_lcbor: entity tri.tri_lcbor
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generic map (expand_type => expand_type )
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port map( clkoff_b => lcb_clkoff_dc_b,
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thold => lcb_cfg_slp_sl_thold_0,
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sg => lcb_sg_0,
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act_dis => lcb_act_dis_dc,
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forcee => mode_force,
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thold_b => mode_thold_b
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);
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mode_lcb: entity tri.tri_lcbnd
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generic map (expand_type => expand_type )
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port map( act => tieup, -- not power saved
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vd => vd,
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gd => gd,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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nclk => nclk,
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forcee => mode_force,
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sg => lcb_sg_0,
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thold_b => mode_thold_b,
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d1clk => mode_d1clk,
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d2clk => mode_d2clk,
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lclk => mode_lclk
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);
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scom_mode_lcb: entity tri.tri_lcbnd
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generic map (expand_type => expand_type )
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port map( act => sc_active, -- active during scom access
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vd => vd,
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gd => gd,
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delay_lclkr => lcb_delay_lclkr_dc,
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mpw1_b => lcb_mpw1_dc_b,
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mpw2_b => lcb_mpw2_dc_b,
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nclk => nclk,
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forcee => mode_force,
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sg => lcb_sg_0,
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thold_b => mode_thold_b,
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d1clk => scom_mode_d1clk,
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d2clk => scom_mode_d2clk,
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lclk => scom_mode_lclk
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);
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----------------------------------------------------------------------
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-- Mode Registers
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----------------------------------------------------------------------
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fir_action0 : entity tri.tri_nlat_scan
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generic map( width => width, init => fir_action0_init, expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => scom_mode_d1clk
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, d2clk => scom_mode_d2clk
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, lclk => scom_mode_lclk
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, scan_in => mode_si(0 to width-1)
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, scan_out => mode_so(0 to width-1)
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, din => fir_action0_in
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, q => fir_action0_lt
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);
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fir_action0_par : entity tri.tri_nlat_scan
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generic map( width => 1, init => fir_action0_par_init, expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => scom_mode_d1clk
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, d2clk => scom_mode_d2clk
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, lclk => scom_mode_lclk
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, scan_in => mode_si(width to width)
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, scan_out => mode_so(width to width)
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, din(0) => fir_action0_par_in
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, q(0) => fir_action0_par_lt
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);
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fir_action1 : entity tri.tri_nlat_scan
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generic map( width => width, init => fir_action1_init, expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => scom_mode_d1clk
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, d2clk => scom_mode_d2clk
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, lclk => scom_mode_lclk
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, scan_in => mode_si(width+1 to 2*width)
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, scan_out => mode_so(width+1 to 2*width)
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, din => fir_action1_in
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, q => fir_action1_lt
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);
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fir_action1_par : entity tri.tri_nlat_scan
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generic map( width => 1, init => fir_action1_par_init, expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => scom_mode_d1clk
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, d2clk => scom_mode_d2clk
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, lclk => scom_mode_lclk
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, scan_in => mode_si(2*width+1 to 2*width+1)
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, scan_out => mode_so(2*width+1 to 2*width+1)
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, din(0) => fir_action1_par_in
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, q(0) => fir_action1_par_lt
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);
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fir_mask : ENTITY tri.tri_nlat_scan
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GENERIC MAP( width => width, init => fir_mask_init, expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => scom_mode_d1clk
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, d2clk => scom_mode_d2clk
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, lclk => scom_mode_lclk
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, scan_in => mode_si(2*width+2 to 3*width+1)
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, scan_out => mode_so(2*width+2 to 3*width+1)
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, din => fir_mask_in
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, q => fir_mask_lt
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);
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fir_mask_par : entity tri.tri_nlat_scan
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generic map( width => 1, init => fir_mask_par_init, expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => scom_mode_d1clk
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, d2clk => scom_mode_d2clk
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, lclk => scom_mode_lclk
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, scan_in => mode_si(3*width+2 to 3*width+2)
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, scan_out => mode_so(3*width+2 to 3*width+2)
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, din(0) => fir_mask_par_in
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, q(0) => fir_mask_par_lt
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);
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fir : entity tri.tri_nlat_scan
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generic map( width => width, init => fir_init, expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => mode_d1clk
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, d2clk => mode_d2clk
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, lclk => mode_lclk
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, scan_in => mode_si(3*width+3 to 4*width+2)
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, scan_out => mode_so(3*width+3 to 4*width+2)
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, din => fir_in
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, q => fir_lt
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);
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----------------------------------------------------------------------
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-- Func Registers with no power savings
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----------------------------------------------------------------------
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sys_xstop : entity tri.tri_nlat
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generic map( width => 1, init => "0", expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => func_d1clk
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, d2clk => func_d2clk
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, lclk => func_lclk
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, scan_in => func_si(1)
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, scan_out => func_so(1)
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, din(0) => sys_xstop_in
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, q(0) => sys_xstop_lt
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);
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recov : entity tri.tri_nlat
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generic map( width => 1, init => "0", expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => func_d1clk
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, d2clk => func_d2clk
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, lclk => func_lclk
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, scan_in => func_si(2)
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, scan_out => func_so(2)
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, din(0) => recov_in
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, q(0) => recov_lt
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);
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xstop : entity tri.tri_nlat
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generic map( width => 1, init => "0", expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => func_d1clk
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, d2clk => func_d2clk
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, lclk => func_lclk
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, scan_in => func_si(3)
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, scan_out => func_so(3)
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, din(0) => xstop_in
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, q(0) => xstop_lt
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);
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trace_err : entity tri.tri_nlat
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generic map( width => 1, init => "0", expand_type => expand_type )
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port map
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( vd => vd
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, gd => gd
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, d1clk => func_d1clk
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, d2clk => func_d2clk
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, lclk => func_lclk
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, scan_in => func_si(4)
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, scan_out => func_so(4)
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, din(0) => trace_error_in
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, q(0) => trace_error_lt
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);
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|
|
|
|
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--******************************************************
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--* Optional Recovery Reset
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--******************************************************
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use_recov_reset_yes: if (use_recov_reset = true) generate
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fir_reset <= NOT gate_AND(recov_reset, NOT fir_action0_lt AND fir_action1_lt);
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end generate use_recov_reset_yes;
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|
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use_recov_reset_no: if (use_recov_reset = false) generate
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fir_reset <= (others => '1') ;
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end generate use_recov_reset_no;
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|
|
|
|
|
--******************************************************
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|
--* FIR
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|
--******************************************************
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-- write to x'0' to write FIR directly
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-- write to x'1' to And-Mask FIR
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-- write to x'2' to Or-Mask FIR
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or_fir_load <= (sc_addr_v(0) or sc_addr_v(2)) and sc_wr_q;
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and_fir_ones <= not((sc_addr_v(0) or sc_addr_v(1)) and sc_wr_q);
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and_fir_load <= sc_addr_v(1) and sc_wr_q;
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|
|
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or_fir <= gate_and( or_fir_load, sc_wdata);
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|
|
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and_fir <= gate_and(and_fir_load, sc_wdata) or
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gate_and(and_fir_ones, data_ones );
|
|
|
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fir_in <= gate_and(not block_fir, error_input) or or_fir or (fir_lt and and_fir and fir_reset);
|
|
|
|
|
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fir_error_in_reef <= error_in; -- does a signal rename for the reef tool
|
|
error_input <= fir_error_in_reef;
|
|
|
|
|
|
--******************************************************
|
|
--* FIR Mask
|
|
--******************************************************
|
|
-- write to x'6' to write FIR-MASK directly
|
|
-- write to x'7' to And-Mask FIR-MASK
|
|
-- write to x'8' to Or-Mask FIR-MASK
|
|
or_mask_load <= (sc_addr_v(6) or sc_addr_v(8)) and sc_wr_q;
|
|
and_mask_ones <= not((sc_addr_v(6) or sc_addr_v(7)) and sc_wr_q);
|
|
and_mask_load <= sc_addr_v(7) and sc_wr_q;
|
|
|
|
or_mask <= gate_and( or_mask_load, sc_wdata);
|
|
and_mask <= gate_and(and_mask_load, sc_wdata) or gate_and(and_mask_ones, data_ones);
|
|
|
|
fir_mask_in <= or_mask or (fir_mask_lt and and_mask);
|
|
fir_mask_par_in <= parity_gen_even(fir_mask_in) when (gate_and(sc_wr_q, or_reduce(sc_addr_v(6 to 8))))='1' else
|
|
fir_mask_par_lt;
|
|
|
|
fir_mask_par_err <= (xor_reduce(fir_mask_lt) xor fir_mask_par_lt) or
|
|
(sc_wr_q and or_reduce(sc_addr_v(6 to 8)) and sc_parity_error_inject);
|
|
|
|
masked <= fir_mask_lt;
|
|
|
|
|
|
--******************************************************
|
|
--* Action Registers
|
|
--******************************************************
|
|
-- write to x'3' to write FIR-Action0 directly
|
|
fir_action0_in <= sc_wdata when (sc_addr_v(3) and sc_wr_q) = '1' else fir_action0_lt;
|
|
fir_action0_par_in <= sc_wparity when (sc_addr_v(3) and sc_wr_q) = '1' else fir_action0_par_lt;
|
|
fir_action0_par_err <= xor_reduce(fir_action0_lt) xor fir_action0_par_lt;
|
|
|
|
-- write to x'4' to write FIR-Action1 directly
|
|
fir_action1_in <= sc_wdata when (sc_addr_v(4) and sc_wr_q) = '1' else fir_action1_lt;
|
|
fir_action1_par_in <= sc_wparity when (sc_addr_v(4) and sc_wr_q) = '1' else fir_action1_par_lt;
|
|
fir_action1_par_err <= xor_reduce(fir_action1_lt) xor fir_action1_par_lt;
|
|
|
|
|
|
--******************************************************
|
|
--* Summary
|
|
--******************************************************
|
|
xstop_in <= or_reduce(fir_lt and fir_action0_lt and not fir_action1_lt and not masked); -- fir_action = 10
|
|
recov_in <= or_reduce(fir_lt and not fir_action0_lt and fir_action1_lt and not masked); -- fir_action = 01
|
|
|
|
block_fir <= xstop_lt or sys_xstop_lt;
|
|
|
|
xstop_err <= xstop_lt;
|
|
recov_err <= recov_lt;
|
|
trace_error <= trace_error_lt;
|
|
|
|
fir_out <= fir_lt;
|
|
act0_out <= fir_action0_lt;
|
|
act1_out <= fir_action1_lt;
|
|
mask_out <= fir_mask_lt;
|
|
|
|
fir_parity_check <= fir_action0_par_err & fir_action1_par_err & fir_mask_par_err;
|
|
|
|
|
|
|
|
--******************************************************
|
|
--* SCOM read logic
|
|
--******************************************************
|
|
sc_rdata <= gate_and(sc_addr_v(0), fir_lt ) or
|
|
gate_and(sc_addr_v(3), fir_action0_lt) or
|
|
gate_and(sc_addr_v(4), fir_action1_lt) or
|
|
gate_and(sc_addr_v(6), fir_mask_lt ) ;
|
|
|
|
|
|
--******************************************************
|
|
--* Optional MCHK Enable Register and Output
|
|
--******************************************************
|
|
mchkgen: if (impl_lxstop_mchk = true) generate
|
|
yes: block
|
|
signal lxstop_mchk_in : std_ulogic;
|
|
signal lxstop_mchk_lt : std_ulogic;
|
|
begin
|
|
|
|
lxstop_mchk_in <= or_reduce(fir_lt and fir_action0_lt and fir_action1_lt and not masked); -- fir_action = 11
|
|
lxstop_mchk <= lxstop_mchk_lt;
|
|
|
|
trace_error_in <= xstop_in or recov_in or lxstop_mchk_in;
|
|
|
|
mchk : entity tri.tri_nlat
|
|
generic map( width => 1, init => "0", expand_type => expand_type )
|
|
port map
|
|
( d1clk => func_d1clk
|
|
, vd => vd
|
|
, gd => gd
|
|
, lclk => func_lclk
|
|
, d2clk => func_d2clk
|
|
, scan_in => func_si(0)
|
|
, scan_out => func_so(0)
|
|
, din(0) => lxstop_mchk_in
|
|
, q(0) => lxstop_mchk_lt
|
|
);
|
|
end block yes;
|
|
end generate mchkgen;
|
|
|
|
nomchk: if (impl_lxstop_mchk = false) generate
|
|
trace_error_in <= xstop_in or recov_in;
|
|
lxstop_mchk <= '0';
|
|
func_so(0) <= func_si(0);
|
|
end generate nomchk;
|
|
|
|
|
|
--******************************************************
|
|
-- Scan Chain Connections
|
|
--******************************************************
|
|
mode_si <= mode_scan_siv;
|
|
mode_scan_sov <= mode_so;
|
|
|
|
func_si <= func_scan_siv;
|
|
func_scan_sov <= func_so;
|
|
|
|
|
|
-----------------------------------------------------------------------
|
|
end pcq_local_fir2;
|