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63 lines
2.4 KiB
VHDL
63 lines
2.4 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--
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-- Description: Core PSRO Sensor
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--
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all ;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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entity pcq_psro_soft is
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port (
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vdd : inout power_logic; -- Local Voltage Grid
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gnd : inout power_logic; -- Local Gnd
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pcq_psro_enable : in std_ulogic_vector(0 to 2); -- from perv
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psro_pcq_ringsig : out std_ulogic -- to the PBus, these need to be triple buffered
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);
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end pcq_psro_soft;
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architecture pcq_psro_soft of pcq_psro_soft is
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begin
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pcq_init: entity tri.tri_psro_soft
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port map
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( vdd => vdd ,
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gnd => gnd ,
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psro_enable => pcq_psro_enable(0 to 2) ,
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psro_ringsig => psro_pcq_ringsig );
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end pcq_psro_soft;
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