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94 lines
3.6 KiB
VHDL
94 lines
3.6 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all ;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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-- input phase is important
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-- (change X (B) by switching xor/xnor )
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entity xuq_add_csmux is port(
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sum_0 :in std_ulogic_vector(0 to 7) ; -- after xor
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sum_1 :in std_ulogic_vector(0 to 7) ;
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ci_b :in std_ulogic ;
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sum :out std_ulogic_vector(0 to 7)
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);
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END xuq_add_csmux;
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ARCHITECTURE xuq_add_csmux OF xuq_add_csmux IS
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal sum0_b, sum1_b :std_ulogic_vector(0 to 7);
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signal int_ci, int_ci_t, int_ci_b :std_ulogic;
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BEGIN
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u_ci: int_ci <= not ci_b;
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u_cit: int_ci_t <= not ci_b;
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u_cib: int_ci_b <= not int_ci_t;
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u_sum0_0: sum0_b(0) <= not( sum_0(0) and int_ci_b );
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u_sum0_1: sum0_b(1) <= not( sum_0(1) and int_ci_b );
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u_sum0_2: sum0_b(2) <= not( sum_0(2) and int_ci_b );
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u_sum0_3: sum0_b(3) <= not( sum_0(3) and int_ci_b );
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u_sum0_4: sum0_b(4) <= not( sum_0(4) and int_ci_b );
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u_sum0_5: sum0_b(5) <= not( sum_0(5) and int_ci_b );
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u_sum0_6: sum0_b(6) <= not( sum_0(6) and int_ci_b );
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u_sum0_7: sum0_b(7) <= not( sum_0(7) and int_ci_b );
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u_sum1_0: sum1_b(0) <= not( sum_1(0) and int_ci );
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u_sum1_1: sum1_b(1) <= not( sum_1(1) and int_ci );
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u_sum1_2: sum1_b(2) <= not( sum_1(2) and int_ci );
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u_sum1_3: sum1_b(3) <= not( sum_1(3) and int_ci );
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u_sum1_4: sum1_b(4) <= not( sum_1(4) and int_ci );
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u_sum1_5: sum1_b(5) <= not( sum_1(5) and int_ci );
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u_sum1_6: sum1_b(6) <= not( sum_1(6) and int_ci );
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u_sum1_7: sum1_b(7) <= not( sum_1(7) and int_ci );
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u_sum_0: sum(0) <= not( sum0_b(0) and sum1_b(0) );
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u_sum_1: sum(1) <= not( sum0_b(1) and sum1_b(1) );
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u_sum_2: sum(2) <= not( sum0_b(2) and sum1_b(2) );
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u_sum_3: sum(3) <= not( sum0_b(3) and sum1_b(3) );
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u_sum_4: sum(4) <= not( sum0_b(4) and sum1_b(4) );
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u_sum_5: sum(5) <= not( sum0_b(5) and sum1_b(5) );
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u_sum_6: sum(6) <= not( sum0_b(6) and sum1_b(6) );
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u_sum_7: sum(7) <= not( sum0_b(7) and sum1_b(7) );
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END; -- ARCH xuq_add_csmux
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