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93 lines
3.3 KiB
VHDL
93 lines
3.3 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all ;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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-- input phase is important
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-- (change X (B) by switching xor/xnor )
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entity xuq_add_glbloc is port(
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g01 :in std_ulogic_vector(0 to 7) ; -- after xor
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t01 :in std_ulogic_vector(0 to 7) ;
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g08 :out std_ulogic ;
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t08 :out std_ulogic
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);
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END xuq_add_glbloc;
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ARCHITECTURE xuq_add_glbloc OF xuq_add_glbloc IS
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal g02_b, t02_b :std_ulogic_vector(0 to 3);
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signal g04, t04 :std_ulogic_vector(0 to 1);
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signal g08_b, t08_b :std_ulogic;
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BEGIN
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u_g02_0: g02_b(0) <= not ( g01(0) or ( t01(0) and g01(1) ) );
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u_g02_1: g02_b(1) <= not ( g01(2) or ( t01(2) and g01(3) ) );
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u_g02_2: g02_b(2) <= not ( g01(4) or ( t01(4) and g01(5) ) );
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u_g02_3: g02_b(3) <= not ( g01(6) or ( t01(6) and g01(7) ) );
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u_t02_0: t02_b(0) <= not ( t01(0) and t01(1) ) ;
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u_t02_1: t02_b(1) <= not ( t01(2) and t01(3) ) ;
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u_t02_2: t02_b(2) <= not ( t01(4) and t01(5) ) ;
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u_t02_3: t02_b(3) <= not ( t01(6) and t01(7) ) ;
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u_g04_0: g04(0) <= not ( g02_b(0) and ( t02_b(0) or g02_b(1) ) ) ;
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u_g04_1: g04(1) <= not ( g02_b(2) and ( t02_b(2) or g02_b(3) ) ) ;
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u_t04_0: t04(0) <= not ( t02_b(0) or t02_b(1) ) ;
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u_t04_1: t04(1) <= not ( t02_b(2) or t02_b(3) ) ;
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u_g08_y: g08_b <= not ( g04(0) or ( t04(0) and g04(1) ) ) ;
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u_t08_y: t08_b <= not ( ( t04(0) and t04(1)) ) ;
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u_g08_x: g08 <= not ( g08_b ) ; -- output
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u_t08_x: t08 <= not ( t08_b ) ; -- output
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END; -- ARCH xuq_add_glbloc
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