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107 lines
3.5 KiB
VHDL
107 lines
3.5 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity xuq_alu_mult_boothdcd is
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port(
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i0 : in std_ulogic;
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i1 : in std_ulogic;
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i2 : in std_ulogic;
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s_neg : out std_ulogic;
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s_x : out std_ulogic;
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s_x2 : out std_ulogic);
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end xuq_alu_mult_boothdcd;
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architecture xuq_alu_mult_boothdcd of xuq_alu_mult_boothdcd is
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signal s_add :std_ulogic;
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signal sx1_a0_b :std_ulogic;
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signal sx1_a1_b :std_ulogic;
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signal sx1_t :std_ulogic;
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signal sx1_i :std_ulogic;
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signal sx2_a0_b :std_ulogic;
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signal sx2_a1_b :std_ulogic;
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signal sx2_t :std_ulogic;
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signal sx2_i :std_ulogic;
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signal i0_b, i1_b, i2_b :std_ulogic;
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begin
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-- i0:2 booth recode table
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----------------------------------
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-- 000 add sh1=0 sh2=0 sub_adj=0
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-- 001 add sh1=1 sh2=0 sub_adj=0
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-- 010 add sh1=1 sh2=0 sub_adj=0
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-- 011 add sh1=0 sh2=1 sub_adj=0
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-- 100 sub sh1=0 sh2=1 sub_adj=1
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-- 101 sub sh1=1 sh2=0 sub_adj=1
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-- 110 sub sh1=1 sh2=0 sub_adj=1
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-- 111 sub sh1=0 sh2=0 sub_adj=0
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-- logically correct
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------------------------------------
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-- s_neg <= (i0);
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-- s_x <= ( not i1 and i2) or ( i1 and not i2);
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-- s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2);
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u_0i: i0_b <= not( i0 );
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u_1i: i1_b <= not( i1 );
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u_2i: i2_b <= not( i2 );
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u_add: s_add <= not( i0 );
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u_sub: s_neg <= not( s_add );
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u_sx1_a0: sx1_a0_b <= not( i1_b and i2 ) ;
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u_sx1_a1: sx1_a1_b <= not( i1 and i2_b ) ;
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u_sx1_t: sx1_t <= not( sx1_a0_b and sx1_a1_b ) ;
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u_sx1_i: sx1_i <= not( sx1_t );
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u_sx1_ii: s_x <= not( sx1_i );
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u_sx2_a0: sx2_a0_b <= not( i0 and i1_b and i2_b ) ;
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u_sx2_a1: sx2_a1_b <= not( i0_b and i1 and i2 ) ;
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u_sx2_t: sx2_t <= not( sx2_a0_b and sx2_a1_b ) ;
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u_sx2_i: sx2_i <= not( sx2_t );
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u_sx2_ii: s_x2 <= not( sx2_i );
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end;
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