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806 lines
44 KiB
VHDL
806 lines
44 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU XER Bypass Unit
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--
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_function_support.all;
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use tri.tri_latches_pkg.all;
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use support.power_logic_pkg.all;
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use work.xuq_pkg.all;
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entity xuq_byp_xer is
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generic (
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threads : integer := 4;
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expand_type : integer := 2;
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regsize : integer := 64);
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port (
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-- Clocks
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nclk : in clk_logic;
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-- Power
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vdd : inout power_logic;
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gnd : inout power_logic;
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trace_bus_enable : in std_ulogic;
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-- Pervasive
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d_mode_dc : in std_ulogic;
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delay_lclkr_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic;
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mpw2_dc_b : in std_ulogic;
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func_sl_force : in std_ulogic;
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func_sl_thold_0_b : in std_ulogic;
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func_slp_sl_force : in std_ulogic;
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func_slp_sl_thold_0_b : in std_ulogic;
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sg_0 : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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-- Used bit signals
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dec_byp_rf1_ca_used : in std_ulogic;
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dec_byp_rf1_ov_used : in std_ulogic;
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-- Bypass Inputs
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rf1_tid : in std_ulogic_vector(0 to threads-1);
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ex5_tid : in std_ulogic_vector(0 to threads-1);
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-- Valid
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dec_byp_ex3_val : in std_ulogic_vector(0 to threads-1);
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dec_byp_rf1_byp_val : in std_ulogic_vector(2 to 3);
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-- Flushes
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xu_ex3_flush : in std_ulogic_vector(0 to threads-1);
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xu_ex4_flush : in std_ulogic_vector(0 to threads-1);
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xu_ex5_flush : in std_ulogic_vector(0 to threads-1);
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-- mfxer
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byp_ex5_xer_rt : out std_ulogic_vector(54 to 63);
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-- Valids
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alu_ex2_div_done : in std_ulogic;
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alu_ex4_mul_done : in std_ulogic;
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-- XER Inputs
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alu_byp_ex2_xer : in std_ulogic_vector(0 to 3); -- 0: OV bit 1: CA bit 2: OV Update 3: CA Update
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alu_byp_ex5_xer_mul : in std_ulogic_vector(0 to 3); -- 0: OV bit 1: CA bit 2: OV Update 3: CA Update
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alu_byp_ex3_xer_div : in std_ulogic_vector(0 to 3); -- 0: OV bit 1: CA bit 2: OV Update 3: CA Update
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spr_byp_ex4_is_mtxer : in std_ulogic_vector(0 to threads-1);
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byp_ex5_mtcrxer : in std_ulogic_vector(32 to 63);
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-- Outputs
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byp_xer_si : out std_ulogic_vector(0 to 7*threads-1);
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byp_xer_so : out std_ulogic_vector(0 to threads-1);
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xer_cr_ex1_xer_ov_in_pipe : out std_ulogic;
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xer_cr_ex2_xer_ov_in_pipe : out std_ulogic;
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xer_cr_ex3_xer_ov_in_pipe : out std_ulogic;
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xer_cr_ex5_xer_ov_in_pipe : out std_ulogic;
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byp_dec_rf1_xer_ca : out std_ulogic;
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xer_debug : out std_ulogic_vector(22 to 87)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_byp_xer;
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architecture xuq_byp_xer of xuq_byp_xer is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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subtype s2 is std_ulogic_vector(0 to 1);
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-- Signals
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signal ex2_xer : std_ulogic_vector(0 to 3);
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signal ex3_xer : std_ulogic_vector(0 to 3);
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signal ex4_xer : std_ulogic_vector(0 to 3);
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signal ex5_xer : std_ulogic_vector(0 to 3);
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signal ex3_val : std_ulogic_vector(0 to threads-1);
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signal ex4_val : std_ulogic_vector(0 to threads-1);
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signal ex5_val : std_ulogic_vector(0 to threads-1);
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signal xer_out : std_ulogic_vector(0 to 10*threads-1);
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signal rf1_byp_val : std_ulogic_vector(4 to 5);
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signal rf1_byp_val_ov : std_ulogic_vector(2 to 5);
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signal rf1_byp_ov_pri : std_ulogic_vector(2 to 6);
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signal rf1_byp_val_ca : std_ulogic_vector(2 to 5);
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signal rf1_byp_ca_pri : std_ulogic_vector(2 to 6);
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signal xer_ex5_mux : std_ulogic_vector(54 to 63);
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signal xer_rf1_mux : std_ulogic_vector(54 to 63);
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signal rf1_ov_byp_from_reg : std_ulogic;
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signal rf1_ov : std_ulogic;
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signal rf1_ca : std_ulogic;
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signal rf1_xer_ov_in_pipe : std_ulogic;
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-- Latches
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signal ex3_xer_q : std_ulogic_vector(0 to 3);
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signal ex4_xer_q : std_ulogic_vector(0 to 3);
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signal ex5_xer_q : std_ulogic_vector(0 to 3);
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signal ex4_val_q : std_ulogic_vector(0 to threads-1);
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signal ex5_val_q : std_ulogic_vector(0 to threads-1);
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signal ex1_xer_ov_bypassed_q : std_ulogic;
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signal ex2_xer_ov_bypassed_q : std_ulogic;
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signal ex3_xer_ov_bypassed_q : std_ulogic;
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signal ex4_xer_ov_bypassed_q : std_ulogic;
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signal ex5_xer_ov_bypassed_q : std_ulogic;
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signal ex1_ov_byp_from_reg_q : std_ulogic;
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signal ex2_ov_byp_from_reg_q : std_ulogic;
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signal ex3_ov_byp_from_reg_q : std_ulogic;
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signal ex4_ov_byp_from_reg_q : std_ulogic;
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signal ex5_ov_byp_from_reg_q : std_ulogic;
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signal ex1_xer_ov_in_pipe_q : std_ulogic;
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signal ex2_xer_ov_in_pipe_q : std_ulogic;
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signal ex3_xer_ov_in_pipe_q : std_ulogic;
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signal ex4_xer_ov_in_pipe_q : std_ulogic;
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signal ex5_xer_ov_in_pipe_q : std_ulogic;
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signal ex5_is_mtxer_q : std_ulogic_vector(0 to threads-1); -- spr_byp_ex4_is_mtxer
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signal ex3_div_done_q : std_ulogic; -- input=>alu_ex2_div_done
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signal ex5_mul_done_q : std_ulogic; -- input=>alu_ex4_mul_done
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signal debug_q, debug_d : std_ulogic_vector(0 to 31); -- input=>debug_d, act=>trace_bus_enable, sleep=>Y, needs_sreset=>0
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-- Scanchains
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constant ex3_xer_offset : integer := 0;
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constant ex4_xer_offset : integer := ex3_xer_offset + ex3_xer_q'length;
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constant ex5_xer_offset : integer := ex4_xer_offset + ex4_xer_q'length;
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constant ex4_val_offset : integer := ex5_xer_offset + ex5_xer_q'length;
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constant ex5_val_offset : integer := ex4_val_offset + ex4_val_q'length;
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constant ex1_xer_ov_bypassed_offset : integer := ex5_val_offset + ex5_val_q'length;
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constant ex2_xer_ov_bypassed_offset : integer := ex1_xer_ov_bypassed_offset + 1;
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constant ex3_xer_ov_bypassed_offset : integer := ex2_xer_ov_bypassed_offset + 1;
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constant ex4_xer_ov_bypassed_offset : integer := ex3_xer_ov_bypassed_offset + 1;
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constant ex5_xer_ov_bypassed_offset : integer := ex4_xer_ov_bypassed_offset + 1;
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constant ex1_ov_byp_from_reg_offset : integer := ex5_xer_ov_bypassed_offset + 1;
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constant ex2_ov_byp_from_reg_offset : integer := ex1_ov_byp_from_reg_offset + 1;
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constant ex3_ov_byp_from_reg_offset : integer := ex2_ov_byp_from_reg_offset + 1;
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constant ex4_ov_byp_from_reg_offset : integer := ex3_ov_byp_from_reg_offset + 1;
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constant ex5_ov_byp_from_reg_offset : integer := ex4_ov_byp_from_reg_offset + 1;
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constant ex1_xer_ov_in_pipe_offset : integer := ex5_ov_byp_from_reg_offset + 1;
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constant ex2_xer_ov_in_pipe_offset : integer := ex1_xer_ov_in_pipe_offset + 1;
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constant ex3_xer_ov_in_pipe_offset : integer := ex2_xer_ov_in_pipe_offset + 1;
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constant ex4_xer_ov_in_pipe_offset : integer := ex3_xer_ov_in_pipe_offset + 1;
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constant ex5_xer_ov_in_pipe_offset : integer := ex4_xer_ov_in_pipe_offset + 1;
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constant ex5_is_mtxer_offset : integer := ex5_xer_ov_in_pipe_offset + 1;
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constant xer_offset : integer := ex5_is_mtxer_offset + ex5_is_mtxer_q'length;
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constant ex3_div_done_offset : integer := xer_offset + 10*threads;
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constant ex5_mul_done_offset : integer := ex3_div_done_offset + 1;
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constant debug_offset : integer := ex5_mul_done_offset + 1;
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constant scan_right : integer := debug_offset + debug_q'length;
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signal siv : std_ulogic_vector(0 to scan_right-1);
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signal sov : std_ulogic_vector(0 to scan_right-1);
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begin
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---------------------------------------------------------------------
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-- Valids
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---------------------------------------------------------------------
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ex3_val <= dec_byp_ex3_val and not xu_ex3_flush;
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ex4_val <= ex4_val_q and not xu_ex4_flush;
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ex5_val <= ex5_val_q and not xu_ex5_flush;
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---------------------------------------------------------------------
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-- XER pipeline input
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---------------------------------------------------------------------
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ex2_xer <= alu_byp_ex2_xer;
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with ex3_div_done_q select
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ex3_xer <= alu_byp_ex3_xer_div when '1',
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ex3_xer_q when others;
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ex4_xer <= ex4_xer_q;
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with ex5_mul_done_q select
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ex5_xer <= alu_byp_ex5_xer_mul when '1',
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ex5_xer_q when others;
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---------------------------------------------------------------------
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-- MFXER
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---------------------------------------------------------------------
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xer_ex5_mux <= mux_t(xer_out,ex5_tid);
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byp_ex5_xer_rt <= (xer_ex5_mux(54) or (ex5_xer_ov_bypassed_q and not ex5_ov_byp_from_reg_q)) & -- SO bit
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(xer_ex5_mux(55) or ex5_xer_ov_bypassed_q) & -- OV bit
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xer_ex5_mux(56 to 63);
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---------------------------------------------------------------------
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-- Bypass valids
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---------------------------------------------------------------------
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rf1_byp_val(4) <= '1' when rf1_tid = ex4_val_q else '0';
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rf1_byp_val(5) <= '1' when rf1_tid = ex5_val_q else '0';
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---------------------------------------------------------------------
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-- Bypass control (OV)
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---------------------------------------------------------------------
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rf1_byp_val_ov(2) <= ex2_xer(2) and dec_byp_rf1_byp_val(2) and dec_byp_rf1_ov_used; -- OV bit in EX2 is valid, TID is valid, OV bit is used in RF1 instr
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rf1_byp_val_ov(3) <= ex3_xer(2) and dec_byp_rf1_byp_val(3) and dec_byp_rf1_ov_used; -- OV bit in EX3 is valid, TID is valid, OV bit is used in RF1 instr
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rf1_byp_val_ov(4) <= ex4_xer(2) and rf1_byp_val(4) and dec_byp_rf1_ov_used; -- OV bit in EX4 is valid, TID is valid, OV bit is used in RF1 instr
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rf1_byp_val_ov(5) <= ex5_xer(2) and rf1_byp_val(5) and dec_byp_rf1_ov_used; -- OV bit in EX5 is valid, TID is valid, OV bit is used in RF1 instr
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-- Prioritization
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rf1_byp_ov_pri(2) <= rf1_byp_val_ov(2);
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rf1_byp_ov_pri(3) <= not rf1_byp_val_ov(2) and rf1_byp_val_ov(3);
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rf1_byp_ov_pri(4) <= not or_reduce(rf1_byp_val_ov(2 to 3)) and rf1_byp_val_ov(4);
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rf1_byp_ov_pri(5) <= not or_reduce(rf1_byp_val_ov(2 to 4)) and rf1_byp_val_ov(5);
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rf1_byp_ov_pri(6) <= not or_reduce(rf1_byp_val_ov(2 to 5));
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---------------------------------------------------------------------
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-- Bypass control (CA)
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---------------------------------------------------------------------
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rf1_byp_val_ca(2) <= ex2_xer(3) and dec_byp_rf1_byp_val(2) and dec_byp_rf1_ca_used; -- CA bit in EX2 is valid, TID is valid, CA bit is used in RF1 instr
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rf1_byp_val_ca(3) <= ex3_xer(3) and dec_byp_rf1_byp_val(3) and dec_byp_rf1_ca_used; -- CA bit in EX3 is valid, TID is valid, CA bit is used in RF1 instr
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rf1_byp_val_ca(4) <= ex4_xer(3) and rf1_byp_val(4) and dec_byp_rf1_ca_used; -- CA bit in EX4 is valid, TID is valid, CA bit is used in RF1 instr
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rf1_byp_val_ca(5) <= ex5_xer(3) and rf1_byp_val(5) and dec_byp_rf1_ca_used; -- CA bit in EX5 is valid, TID is valid, CA bit is used in RF1 instr
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-- Prioritization
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rf1_byp_ca_pri(2) <= rf1_byp_val_ca(2);
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rf1_byp_ca_pri(3) <= not rf1_byp_val_ca(2) and rf1_byp_val_ca(3);
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rf1_byp_ca_pri(4) <= not or_reduce(rf1_byp_val_ca(2 to 3)) and rf1_byp_val_ca(4);
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rf1_byp_ca_pri(5) <= not or_reduce(rf1_byp_val_ca(2 to 4)) and rf1_byp_val_ca(5);
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rf1_byp_ca_pri(6) <= not or_reduce(rf1_byp_val_ca(2 to 5));
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---------------------------------------------------------------------
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-- RF1 Source Selection
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---------------------------------------------------------------------
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rf1_ov <= (ex2_xer(0) and rf1_byp_ov_pri(2)) or
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(ex3_xer(0) and rf1_byp_ov_pri(3)) or
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(ex4_xer(0) and rf1_byp_ov_pri(4)) or
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(ex5_xer(0) and rf1_byp_ov_pri(5)) or
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(xer_rf1_mux(55) and rf1_byp_ov_pri(6));
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rf1_ca <= (ex2_xer(1) and rf1_byp_ca_pri(2)) or
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(ex3_xer(1) and rf1_byp_ca_pri(3)) or
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(ex4_xer(1) and rf1_byp_ca_pri(4)) or
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(ex5_xer(1) and rf1_byp_ca_pri(5)) or
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(xer_rf1_mux(56) and rf1_byp_ca_pri(6));
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xer_rf1_mux <= mux_t(xer_out,rf1_tid);
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rf1_ov_byp_from_reg <= rf1_byp_ov_pri(6);
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---------------------------------------------------------------------
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-- XER Writeback
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---------------------------------------------------------------------
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xuq_byp_xer_gen : for t in 0 to threads-1 generate
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signal xer_d, xer_q : std_ulogic_vector(54 to 63);
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signal ex5_mtxer_we : std_ulogic;
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signal ex5_ca_we : std_ulogic;
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signal ex5_ov_we : std_ulogic;
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signal ex5_so_sel : std_ulogic_vector(0 to 2);
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signal ex5_ov_sel : std_ulogic_vector(0 to 2);
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signal ex5_ca_sel : std_ulogic_vector(0 to 2);
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begin
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ex5_mtxer_we <= ex5_val(t) and ex5_is_mtxer_q(t);
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ex5_ov_we <= ex5_val(t) and ex5_xer(2);
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ex5_ca_we <= ex5_val(t) and ex5_xer(3);
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ex5_so_sel(0 to 1) <= ex5_mtxer_we & (ex5_ov_we and ex5_xer(0));
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ex5_so_sel(2) <= not (ex5_so_sel(0) or ex5_so_sel(1));
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ex5_ov_sel(0 to 1) <= ex5_mtxer_we & ex5_ov_we;
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ex5_ov_sel(2) <= not (ex5_ov_sel(0) or ex5_ov_sel(1));
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ex5_ca_sel(0 to 1) <= ex5_mtxer_we & ex5_ca_we;
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ex5_ca_sel(2) <= not (ex5_ca_sel(0) or ex5_ca_sel(1));
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-- SO Bit
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xer_d(54) <= (byp_ex5_mtcrxer(32) and ex5_so_sel(0)) or
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( ex5_so_sel(1)) or
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(xer_q(54) and ex5_so_sel(2));
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-- OV Bit
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xer_d(55) <= (byp_ex5_mtcrxer(33) and ex5_ov_sel(0)) or
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(ex5_xer(0) and ex5_ov_sel(1)) or
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(xer_q(55) and ex5_ov_sel(2));
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-- CA Bit
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xer_d(56) <= (byp_ex5_mtcrxer(34) and ex5_ca_sel(0)) or
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(ex5_xer(1) and ex5_ca_sel(1)) or
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(xer_q(56) and ex5_ca_sel(2));
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-- SI
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xer_d(57 to 63) <= byp_ex5_mtcrxer(57 to 63) when ex5_mtxer_we = '1' else
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xer_q(57 to 63);
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-- XER Output
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xer_out(t*10 to t*10+9) <= xer_q;
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byp_xer_si(t*7 to t*7+6) <= xer_q(57 to 63);
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byp_xer_so(t) <= xer_q(54);
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---------------------------------------------------------------------
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-- XER Latch
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---------------------------------------------------------------------
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xer_latch : tri_rlmreg_p
|
|
generic map (width => xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(xer_offset + xer_q'length*t to xer_offset + xer_q'length*(t+1)-1),
|
|
scout => sov(xer_offset + xer_q'length*t to xer_offset + xer_q'length*(t+1)-1),
|
|
din => xer_d,
|
|
dout => xer_q);
|
|
end generate;
|
|
|
|
---------------------------------------------------------------------
|
|
-- XER output (threadwise)
|
|
---------------------------------------------------------------------
|
|
byp_dec_rf1_xer_ca <= rf1_ca;
|
|
|
|
rf1_xer_ov_in_pipe <= (ex2_xer(0) and ex2_xer(2) and dec_byp_rf1_byp_val(2)) or
|
|
(ex3_xer(0) and ex3_xer(2) and dec_byp_rf1_byp_val(3)) or
|
|
(ex4_xer(0) and ex4_xer(2) and rf1_byp_val(4) ) or
|
|
(ex5_xer(0) and ex5_xer(2) and rf1_byp_val(5) );
|
|
|
|
xer_cr_ex1_xer_ov_in_pipe <= ex1_xer_ov_in_pipe_q;
|
|
xer_cr_ex2_xer_ov_in_pipe <= ex2_xer_ov_in_pipe_q;
|
|
xer_cr_ex3_xer_ov_in_pipe <= ex3_xer_ov_in_pipe_q;
|
|
xer_cr_ex5_xer_ov_in_pipe <= ex5_xer_ov_in_pipe_q;
|
|
|
|
mark_unused(xer_rf1_mux(54));
|
|
mark_unused(xer_rf1_mux(57 to 63));
|
|
mark_unused(byp_ex5_mtcrxer(35 to 56));
|
|
|
|
---------------------------------------------------------------------
|
|
-- Debug
|
|
---------------------------------------------------------------------
|
|
debug_d(0 to 31) <= ex5_val &
|
|
dec_byp_rf1_ov_used &
|
|
dec_byp_rf1_ca_used &
|
|
rf1_byp_ov_pri(2 to 6) &
|
|
rf1_byp_ca_pri(2 to 6) &
|
|
ex2_xer(0 to 3) &
|
|
ex3_xer(0 to 3) &
|
|
ex4_xer(0 to 3) &
|
|
ex5_xer(0 to 3);
|
|
|
|
|
|
xer_debug(22 to 87) <= debug_q &
|
|
ex3_div_done_q &
|
|
ex5_mul_done_q &
|
|
ex5_is_mtxer_q(0 to 3) &
|
|
ex1_xer_ov_bypassed_q &
|
|
ex2_xer_ov_bypassed_q &
|
|
ex3_xer_ov_bypassed_q &
|
|
ex4_xer_ov_bypassed_q &
|
|
ex5_xer_ov_bypassed_q &
|
|
ex1_ov_byp_from_reg_q &
|
|
ex2_ov_byp_from_reg_q &
|
|
ex3_ov_byp_from_reg_q &
|
|
ex4_ov_byp_from_reg_q &
|
|
ex5_ov_byp_from_reg_q &
|
|
ex1_xer_ov_in_pipe_q &
|
|
ex2_xer_ov_in_pipe_q &
|
|
ex3_xer_ov_in_pipe_q &
|
|
ex4_xer_ov_in_pipe_q &
|
|
ex5_xer_ov_in_pipe_q &
|
|
xer_out( 7 to 9) &
|
|
xer_out(17 to 19) &
|
|
xer_out(27 to 29) &
|
|
xer_out(37 to 39) &
|
|
'0';
|
|
|
|
---------------------------------------------------------------------
|
|
-- Latch Instances
|
|
---------------------------------------------------------------------
|
|
ex3_xer_latch : tri_rlmreg_p
|
|
generic map (width => ex3_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex3_xer_offset to ex3_xer_offset + ex3_xer_q'length-1),
|
|
scout => sov(ex3_xer_offset to ex3_xer_offset + ex3_xer_q'length-1),
|
|
din => ex2_xer,
|
|
dout => ex3_xer_q);
|
|
ex4_xer_latch : tri_rlmreg_p
|
|
generic map (width => ex4_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex4_xer_offset to ex4_xer_offset + ex4_xer_q'length-1),
|
|
scout => sov(ex4_xer_offset to ex4_xer_offset + ex4_xer_q'length-1),
|
|
din => ex3_xer,
|
|
dout => ex4_xer_q);
|
|
ex5_xer_latch : tri_rlmreg_p
|
|
generic map (width => ex5_xer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex5_xer_offset to ex5_xer_offset + ex5_xer_q'length-1),
|
|
scout => sov(ex5_xer_offset to ex5_xer_offset + ex5_xer_q'length-1),
|
|
din => ex4_xer,
|
|
dout => ex5_xer_q);
|
|
ex4_val_latch : tri_rlmreg_p
|
|
generic map (width => ex4_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1),
|
|
scout => sov(ex4_val_offset to ex4_val_offset + ex4_val_q'length-1),
|
|
din => ex3_val,
|
|
dout => ex4_val_q);
|
|
ex5_val_latch : tri_rlmreg_p
|
|
generic map (width => ex5_val_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1),
|
|
scout => sov(ex5_val_offset to ex5_val_offset + ex5_val_q'length-1),
|
|
din => ex4_val,
|
|
dout => ex5_val_q);
|
|
ex1_xer_ov_bypassed_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex1_xer_ov_bypassed_offset),
|
|
scout => sov(ex1_xer_ov_bypassed_offset),
|
|
din => rf1_ov,
|
|
dout => ex1_xer_ov_bypassed_q);
|
|
ex2_xer_ov_bypassed_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex2_xer_ov_bypassed_offset),
|
|
scout => sov(ex2_xer_ov_bypassed_offset),
|
|
din => ex1_xer_ov_bypassed_q,
|
|
dout => ex2_xer_ov_bypassed_q);
|
|
ex3_xer_ov_bypassed_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex3_xer_ov_bypassed_offset),
|
|
scout => sov(ex3_xer_ov_bypassed_offset),
|
|
din => ex2_xer_ov_bypassed_q,
|
|
dout => ex3_xer_ov_bypassed_q);
|
|
ex4_xer_ov_bypassed_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex4_xer_ov_bypassed_offset),
|
|
scout => sov(ex4_xer_ov_bypassed_offset),
|
|
din => ex3_xer_ov_bypassed_q,
|
|
dout => ex4_xer_ov_bypassed_q);
|
|
ex5_xer_ov_bypassed_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex5_xer_ov_bypassed_offset),
|
|
scout => sov(ex5_xer_ov_bypassed_offset),
|
|
din => ex4_xer_ov_bypassed_q,
|
|
dout => ex5_xer_ov_bypassed_q);
|
|
ex1_ov_byp_from_reg_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex1_ov_byp_from_reg_offset),
|
|
scout => sov(ex1_ov_byp_from_reg_offset),
|
|
din => rf1_ov_byp_from_reg,
|
|
dout => ex1_ov_byp_from_reg_q);
|
|
ex2_ov_byp_from_reg_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex2_ov_byp_from_reg_offset),
|
|
scout => sov(ex2_ov_byp_from_reg_offset),
|
|
din => ex1_ov_byp_from_reg_q,
|
|
dout => ex2_ov_byp_from_reg_q);
|
|
ex3_ov_byp_from_reg_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex3_ov_byp_from_reg_offset),
|
|
scout => sov(ex3_ov_byp_from_reg_offset),
|
|
din => ex2_ov_byp_from_reg_q,
|
|
dout => ex3_ov_byp_from_reg_q);
|
|
ex4_ov_byp_from_reg_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex4_ov_byp_from_reg_offset),
|
|
scout => sov(ex4_ov_byp_from_reg_offset),
|
|
din => ex3_ov_byp_from_reg_q,
|
|
dout => ex4_ov_byp_from_reg_q);
|
|
ex5_ov_byp_from_reg_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex5_ov_byp_from_reg_offset),
|
|
scout => sov(ex5_ov_byp_from_reg_offset),
|
|
din => ex4_ov_byp_from_reg_q,
|
|
dout => ex5_ov_byp_from_reg_q);
|
|
ex1_xer_ov_in_pipe_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex1_xer_ov_in_pipe_offset),
|
|
scout => sov(ex1_xer_ov_in_pipe_offset),
|
|
din => rf1_xer_ov_in_pipe,
|
|
dout => ex1_xer_ov_in_pipe_q);
|
|
ex2_xer_ov_in_pipe_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex2_xer_ov_in_pipe_offset),
|
|
scout => sov(ex2_xer_ov_in_pipe_offset),
|
|
din => ex1_xer_ov_in_pipe_q,
|
|
dout => ex2_xer_ov_in_pipe_q);
|
|
ex3_xer_ov_in_pipe_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc,
|
|
delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b,
|
|
mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex3_xer_ov_in_pipe_offset),
|
|
scout => sov(ex3_xer_ov_in_pipe_offset),
|
|
din => ex2_xer_ov_in_pipe_q,
|
|
dout => ex3_xer_ov_in_pipe_q);
|
|
ex4_xer_ov_in_pipe_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk,
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vd => vdd,
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gd => gnd,
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act => tiup,
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forcee => func_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ex4_xer_ov_in_pipe_offset),
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scout => sov(ex4_xer_ov_in_pipe_offset),
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din => ex3_xer_ov_in_pipe_q,
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dout => ex4_xer_ov_in_pipe_q);
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ex5_xer_ov_in_pipe_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk,
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vd => vdd,
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gd => gnd,
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act => tiup,
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forcee => func_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ex5_xer_ov_in_pipe_offset),
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scout => sov(ex5_xer_ov_in_pipe_offset),
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din => ex4_xer_ov_in_pipe_q,
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dout => ex5_xer_ov_in_pipe_q);
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ex5_is_mtxer_latch : tri_rlmreg_p
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generic map (width => ex5_is_mtxer_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => tiup,
|
|
forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
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scin => siv(ex5_is_mtxer_offset to ex5_is_mtxer_offset+ex5_is_mtxer_q'length-1),
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scout => sov(ex5_is_mtxer_offset to ex5_is_mtxer_offset+ex5_is_mtxer_q'length-1),
|
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din => spr_byp_ex4_is_mtxer,
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dout => ex5_is_mtxer_q);
|
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ex3_div_done_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex3_div_done_offset),
|
|
scout => sov(ex3_div_done_offset),
|
|
din => alu_ex2_div_done,
|
|
dout => ex3_div_done_q);
|
|
ex5_mul_done_latch : tri_rlmlatch_p
|
|
generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk, vd => vdd, gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(ex5_mul_done_offset),
|
|
scout => sov(ex5_mul_done_offset),
|
|
din => alu_ex4_mul_done,
|
|
dout => ex5_mul_done_q);
|
|
debug_latch : tri_rlmreg_p
|
|
generic map (width => debug_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
|
|
port map (nclk => nclk, vd => vdd, gd => gnd,
|
|
act => trace_bus_enable,
|
|
forcee => func_slp_sl_force,
|
|
d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
|
|
thold_b => func_slp_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(debug_offset to debug_offset + debug_q'length-1),
|
|
scout => sov(debug_offset to debug_offset + debug_q'length-1),
|
|
din => debug_d,
|
|
dout => debug_q);
|
|
|
|
siv(0 to siv'right) <= sov(1 to siv'right) & scan_in;
|
|
scan_out <= sov(0);
|
|
|
|
end architecture xuq_byp_xer;
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