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140 lines
5.7 KiB
VHDL
140 lines
5.7 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU CPL - Configurable Flush Delay Counter
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--
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library ieee,ibm,support,tri;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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entity xuq_cpl_fctr is
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generic(
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expand_type : integer := 2;
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threads : integer := 4;
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clockgate : integer range 0 to 1 := 1;
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passthru : integer range 0 to 1 := 1;
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delay_width : integer := 4);
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port(
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nclk : in clk_logic;
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forcee : in std_ulogic;
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thold_b : in std_ulogic;
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sg : in std_ulogic;
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d_mode : in std_ulogic;
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delay_lclkr : in std_ulogic;
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mpw1_b : in std_ulogic;
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mpw2_b : in std_ulogic;
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scin : in std_ulogic;
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scout : out std_ulogic;
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din : in std_ulogic_vector(0 to threads-1);
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dout : out std_ulogic_vector(0 to threads-1);
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delay : in std_ulogic_vector(0 to delay_width-1);
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vd : inout power_logic;
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gd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_cpl_fctr;
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architecture xuq_cpl_fctr of xuq_cpl_fctr is
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type DELAY_ARR is array (0 to threads-1) of std_ulogic_vector(0 to delay_width-1);
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subtype s2 is std_ulogic_vector(0 to 1);
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-- Latches
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signal delay_q, delay_d : DELAY_ARR;
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-- Scanchains
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constant delay_offset : integer := 0;
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constant scan_right : integer := delay_offset + delay_q(0)'length*threads;
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signal siv : std_ulogic_vector(0 to scan_right-1);
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signal sov : std_ulogic_vector(0 to scan_right-1);
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-- Signals
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signal set,zero_b,act : std_ulogic_vector(0 to threads-1);
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begin
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threads_gen : for t in 0 to threads-1 generate
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signal delay_m1 : std_ulogic_vector(0 to delay_width-1);
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begin
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set(t) <= din(t);
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zero_b(t) <= or_reduce(delay_q(t));
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delay_m1 <= std_ulogic_vector(unsigned(delay_q(t)) - 1);
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clockgate_0 : if clockgate = 0 generate
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act(t) <= '1';
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with s2'(set(t) & zero_b(t)) select
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delay_d(t) <= delay when "11",
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delay when "10",
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delay_m1 when "01",
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delay_q(t) when others;
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end generate;
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clockgate_1 : if clockgate = 1 generate
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act(t) <= set(t) or zero_b(t);
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with set(t) select
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delay_d(t) <= delay when '1',
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delay_m1 when others;
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end generate;
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passthru_gen_1 : if passthru = 1 generate
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dout(t) <= zero_b(t) or din(t);
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end generate;
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passthru_gen_0 : if passthru = 0 generate
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dout(t) <= zero_b(t);
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end generate;
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delay_latch : tri_rlmreg_p
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generic map (width => delay_q(0)'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vd, gd => gd,
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act => act(t),
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forcee => forcee,
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d_mode => d_mode, delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b, mpw2_b => mpw2_b,
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thold_b => thold_b,
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sg => sg,
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scin => siv(delay_offset+delay_q(0)'length*t to delay_offset+delay_q(0)'length*(t+1)-1),
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scout => sov(delay_offset+delay_q(0)'length*t to delay_offset+delay_q(0)'length*(t+1)-1),
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din => delay_d(t),
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dout => delay_q(t));
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end generate;
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siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scin;
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scout <= sov(0);
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end architecture xuq_cpl_fctr;
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