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117 lines
4.0 KiB
VHDL
117 lines
4.0 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: Prioritizer
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--
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library ieee,ibm,support;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_function_support.reverse;
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entity xuq_cpl_pri is
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generic(
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size : integer range 3 to 32 := 32; -- Size of "cond"
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rev : integer range 0 to 1 := 0; -- 0 = 0 is highest, 1 = 0 is lowest
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cmp_zero : integer range 0 to 1 := 0); -- 1 = include comparing cond to zero in pri vector
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port(
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cond : in std_ulogic_vector(0 to size-1);
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pri : out std_ulogic_vector(0 to size-1+cmp_zero);
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or_cond : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_cpl_pri;
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architecture xuq_cpl_pri of xuq_cpl_pri is
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constant s : integer := size-1;
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signal l0 : std_ulogic_vector(0 to s);
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signal or_l1,or_l2,or_l3,or_l4,or_l5: std_ulogic_vector(0 to s);
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begin
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rev_gen0 : if rev = 0 generate
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l0(0 to s) <= cond(0 to s);
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end generate;
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rev_gen1 : if rev = 1 generate
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l0(0 to s) <= reverse(cond(0 to s));
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end generate;
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-- Odd Numbered Levels are inverted
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l1_not: or_l1(0) <= not l0(0);
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l1_nor: or_l1(1 to s) <= l0(0 to s-1) nor l0(1 to s);
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or_l2_gen0 : if s >= 2 generate
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or_l2(0 to 1) <= not or_l1(0 to 1);
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or_l2(2 to s) <= or_l1(2 to s) nand or_l1(0 to s-2);
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end generate;
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or_l2_gen1 : if s < 2 generate
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or_l2 <= not or_l1;
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end generate;
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or_l3_gen0 : if s >= 4 generate
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or_l3(0 to 3) <= not or_l2(0 to 3);
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or_l3(4 to s) <= or_l2(4 to s) nor or_l2(0 to s-4);
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end generate;
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or_l3_gen1 : if s < 4 generate
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or_l3 <= not or_l2;
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end generate;
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or_l4_gen0 : if s >= 8 generate
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or_l4(0 to 7) <= not or_l3(0 to 7);
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or_l4(8 to s) <= or_l3(8 to s) nand or_l3(0 to s-8);
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end generate;
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or_l4_gen1 : if s < 8 generate
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or_l4 <= not or_l3;
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end generate;
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or_l5_gen0 : if s >= 16 generate
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or_l5(0 to 15) <= not or_l4(0 to 15);
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or_l5(16 to s) <= or_l4(16 to s) nor or_l4(0 to s-16);
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end generate;
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or_l5_gen1 : if s < 16 generate
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or_l5 <= not or_l4;
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end generate;
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pri(0) <= cond(0);
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pri(1 to s) <= cond(1 to s) and or_l5(0 to s-1);
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cmp_zero_gen : if cmp_zero = 1 generate
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pri(s+1) <= or_l5(s);
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end generate;
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or_cond <= not or_l5(s);
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end architecture xuq_cpl_pri;
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