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268 lines
12 KiB
VHDL
268 lines
12 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU SPR - Wrapper
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--
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library ieee,ibm,support,work,tri;
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use ieee.std_logic_1164.all;
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use support.power_logic_pkg.all;
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use ibm.std_ulogic_function_support.all;
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use tri.tri_latches_pkg.all;
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entity xuq_cpl_spr is
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generic(
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hvmode : integer := 1;
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a2mode : integer := 1;
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expand_type : integer := 2;
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threads : integer := 4;
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regsize : integer := 64;
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eff_ifar : integer := 62);
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port(
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nclk : in clk_logic;
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d_mode_dc : in std_ulogic;
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delay_lclkr_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic;
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mpw2_dc_b : in std_ulogic;
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dcfg_sl_force : in std_ulogic;
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dcfg_sl_thold_0_b : in std_ulogic;
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func_sl_force : in std_ulogic;
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func_sl_thold_0_b : in std_ulogic;
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func_nsl_force : in std_ulogic;
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func_nsl_thold_0_b : in std_ulogic;
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sg_0 : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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dcfg_scan_in : in std_ulogic;
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dcfg_scan_out : out std_ulogic;
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-- Decode
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spr_bit_act : in std_ulogic;
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exx_act : in std_ulogic_vector(1 to 4);
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ex1_instr : in std_ulogic_vector(11 to 20);
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ex2_tid : in std_ulogic_vector(0 to threads-1);
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ex1_is_mfspr : in std_ulogic;
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ex1_is_mtspr : in std_ulogic;
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ex4_lr_update : in std_ulogic;
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ex4_ctr_dec_update : in std_ulogic;
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-- IFAR
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ex2_ifar : in std_ulogic_vector(0 to eff_ifar*threads-1);
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-- Write Interface
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ex5_val : in std_ulogic_vector(0 to threads-1);
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ex5_spr_wd : in std_ulogic_vector(64-regsize to 63);
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ex5_cia_p1 : in std_ulogic_vector(62-eff_ifar to 61);
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ex2_mtiar : out std_ulogic;
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-- Read Data
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cpl_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63);
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-- IAC Compare
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ex3_iac1_cmpr : out std_ulogic_vector(0 to threads-1);
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ex3_iac2_cmpr : out std_ulogic_vector(0 to threads-1);
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ex3_iac3_cmpr : out std_ulogic_vector(0 to threads-1);
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ex3_iac4_cmpr : out std_ulogic_vector(0 to threads-1);
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-- SPRs
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spr_cpl_iac1_en : in std_ulogic_vector(0 to threads-1);
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spr_cpl_iac2_en : in std_ulogic_vector(0 to threads-1);
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spr_cpl_iac3_en : in std_ulogic_vector(0 to threads-1);
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spr_cpl_iac4_en : in std_ulogic_vector(0 to threads-1);
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spr_dbcr1_iac12m : in std_ulogic_vector(0 to threads-1);
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spr_dbcr1_iac34m : in std_ulogic_vector(0 to threads-1);
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spr_iar : in std_ulogic_vector(0 to eff_ifar*threads-1);
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spr_msr_cm : in std_ulogic_vector(0 to threads-1);
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spr_givpr : out std_ulogic_vector(0 to eff_ifar-10-1);
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spr_ivpr : out std_ulogic_vector(0 to eff_ifar-10-1);
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spr_xucr3_hold1_dly : out std_ulogic_vector(0 to 3);
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spr_xucr3_cm_hold_dly : out std_ulogic_vector(0 to 3);
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spr_xucr3_stop_dly : out std_ulogic_vector(0 to 3);
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spr_xucr3_hold0_dly : out std_ulogic_vector(0 to 3);
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spr_xucr3_csi_dly : out std_ulogic_vector(0 to 3);
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spr_xucr3_int_dly : out std_ulogic_vector(0 to 3);
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spr_xucr3_asyncblk_dly : out std_ulogic_vector(0 to 3);
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spr_xucr3_flush_dly : out std_ulogic_vector(0 to 3);
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spr_xucr4_mmu_mchk : out std_ulogic;
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spr_xucr4_mddmh : out std_ulogic;
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spr_xucr4_div_barr_thres : out std_ulogic_vector(0 to 7);
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spr_xucr4_div_bar_dis : out std_ulogic;
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spr_xucr4_lsu_bar_dis : out std_ulogic;
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spr_xucr4_barr_dly : out std_ulogic_vector(0 to 3);
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spr_ctr : out std_ulogic_vector(0 to (regsize)*threads-1);
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spr_lr : out std_ulogic_vector(0 to (regsize)*threads-1);
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-- Power
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vdd : inout power_logic;
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gnd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_cpl_spr;
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architecture xuq_cpl_spr of xuq_cpl_spr is
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signal siv : std_ulogic_vector(0 to threads);
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signal sov : std_ulogic_vector(0 to threads);
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signal cspr_tspr_ex5_is_mtspr : std_ulogic;
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signal cspr_tspr_ex5_instr : std_ulogic_vector(11 to 20);
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signal cspr_tspr_ex2_instr : std_ulogic_vector(11 to 20);
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signal tspr_cspr_ex2_tspr_rt : std_ulogic_vector(0 to regsize*threads-1);
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begin
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xu_cpl_spr_cspr : entity work.xuq_cpl_spr_cspr(xuq_cpl_spr_cspr)
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generic map(
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hvmode => hvmode,
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a2mode => a2mode,
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expand_type => expand_type,
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threads => threads,
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regsize => regsize,
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eff_ifar => eff_ifar)
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port map(
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nclk => nclk,
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d_mode_dc => d_mode_dc,
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delay_lclkr_dc => delay_lclkr_dc,
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mpw1_dc_b => mpw1_dc_b,
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mpw2_dc_b => mpw2_dc_b,
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dcfg_sl_force => dcfg_sl_force,
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dcfg_sl_thold_0_b => dcfg_sl_thold_0_b,
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func_sl_force => func_sl_force,
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func_sl_thold_0_b => func_sl_thold_0_b,
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func_nsl_force => func_nsl_force,
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func_nsl_thold_0_b => func_nsl_thold_0_b,
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sg_0 => sg_0,
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scan_in => siv(threads),
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scan_out => sov(threads),
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dcfg_scan_in => dcfg_scan_in,
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dcfg_scan_out => dcfg_scan_out,
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-- Decode
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spr_bit_act => spr_bit_act,
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exx_act => exx_act,
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ex1_instr => ex1_instr,
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ex2_tid => ex2_tid,
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ex1_is_mfspr => ex1_is_mfspr,
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ex1_is_mtspr => ex1_is_mtspr,
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-- IFAR
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ex2_ifar => ex2_ifar,
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-- Write Interface
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ex5_valid => ex5_val,
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ex5_spr_wd => ex5_spr_wd,
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ex2_mtiar => ex2_mtiar,
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-- SPRT Interface
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cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr,
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cspr_tspr_ex5_instr => cspr_tspr_ex5_instr,
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cspr_tspr_ex2_instr => cspr_tspr_ex2_instr,
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-- Read Data
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tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt,
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cpl_byp_ex3_spr_rt => cpl_byp_ex3_spr_rt,
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-- IAC Compare
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ex3_iac1_cmpr => ex3_iac1_cmpr,
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ex3_iac2_cmpr => ex3_iac2_cmpr,
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ex3_iac3_cmpr => ex3_iac3_cmpr,
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ex3_iac4_cmpr => ex3_iac4_cmpr,
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-- SPRs
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spr_cpl_iac1_en => spr_cpl_iac1_en,
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spr_cpl_iac2_en => spr_cpl_iac2_en,
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spr_cpl_iac3_en => spr_cpl_iac3_en,
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spr_cpl_iac4_en => spr_cpl_iac4_en,
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spr_dbcr1_iac12m => spr_dbcr1_iac12m,
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spr_dbcr1_iac34m => spr_dbcr1_iac34m,
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spr_msr_cm => spr_msr_cm,
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spr_givpr => spr_givpr,
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spr_ivpr => spr_ivpr,
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spr_xucr3_hold1_dly => spr_xucr3_hold1_dly,
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spr_xucr3_cm_hold_dly => spr_xucr3_cm_hold_dly,
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spr_xucr3_stop_dly => spr_xucr3_stop_dly,
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spr_xucr3_hold0_dly => spr_xucr3_hold0_dly,
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spr_xucr3_csi_dly => spr_xucr3_csi_dly,
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spr_xucr3_int_dly => spr_xucr3_int_dly,
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spr_xucr3_asyncblk_dly => spr_xucr3_asyncblk_dly,
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spr_xucr3_flush_dly => spr_xucr3_flush_dly,
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spr_xucr4_mmu_mchk => spr_xucr4_mmu_mchk,
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spr_xucr4_mddmh => spr_xucr4_mddmh,
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spr_xucr4_div_barr_thres => spr_xucr4_div_barr_thres,
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spr_xucr4_div_bar_dis => spr_xucr4_div_bar_dis,
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spr_xucr4_lsu_bar_dis => spr_xucr4_lsu_bar_dis,
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spr_xucr4_barr_dly => spr_xucr4_barr_dly,
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-- Power
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vdd => vdd,
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gnd => gnd
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);
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thread : for t in 0 to threads-1 generate
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xu_cpl_spr_tspr : entity work.xuq_cpl_spr_tspr(xuq_cpl_spr_tspr)
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generic map(
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hvmode => hvmode,
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a2mode => a2mode,
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expand_type => expand_type,
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regsize => regsize,
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eff_ifar => eff_ifar)
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port map(
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nclk => nclk,
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d_mode_dc => d_mode_dc,
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delay_lclkr_dc => delay_lclkr_dc,
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mpw1_dc_b => mpw1_dc_b,
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mpw2_dc_b => mpw2_dc_b,
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func_sl_force => func_sl_force,
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func_sl_thold_0_b => func_sl_thold_0_b,
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sg_0 => sg_0,
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scan_in => siv(t),
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scan_out => sov(t),
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cspr_tspr_ex2_instr => cspr_tspr_ex2_instr,
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tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt(regsize*t to regsize*(t+1)-1),
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-- Write Interface
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ex5_val => ex5_val(t),
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cspr_tspr_ex5_is_mtspr => cspr_tspr_ex5_is_mtspr,
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cspr_tspr_ex5_instr => cspr_tspr_ex5_instr,
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ex5_spr_wd => ex5_spr_wd,
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ex5_cia_p1 => ex5_cia_p1,
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-- Decode Signals
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ex4_lr_update => ex4_lr_update,
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ex4_ctr_dec_update => ex4_ctr_dec_update,
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-- SPRs
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spr_iar => spr_iar(eff_ifar*t to eff_ifar*(t+1)-1),
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spr_ctr => spr_ctr((regsize)*t to (regsize)*(t+1)-1),
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spr_lr => spr_lr((regsize)*t to (regsize)*(t+1)-1),
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-- Power
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vdd => vdd,
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gnd => gnd
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);
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end generate;
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siv(0 to threads) <= sov(1 to threads) & scan_in;
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scan_out <= sov(0);
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end architecture xuq_cpl_spr;
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