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308 lines
12 KiB
VHDL
308 lines
12 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU SPR - per thread register slice
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--
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library ieee,ibm,support,work,tri;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use support.power_logic_pkg.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use tri.tri_latches_pkg.all;
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use work.xuq_pkg.all;
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entity xuq_cpl_spr_tspr is
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generic(
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hvmode : integer := 1;
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a2mode : integer := 1;
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expand_type : integer := 2;
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regsize : integer := 64;
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eff_ifar : integer := 62);
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port(
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nclk : in clk_logic;
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d_mode_dc : in std_ulogic;
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delay_lclkr_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic;
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mpw2_dc_b : in std_ulogic;
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func_sl_force : in std_ulogic;
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func_sl_thold_0_b : in std_ulogic;
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sg_0 : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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-- Read Interface
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cspr_tspr_ex2_instr : in std_ulogic_vector(11 to 20);
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tspr_cspr_ex2_tspr_rt : out std_ulogic_vector(64-regsize to 63);
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-- Write Interface
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ex5_val : in std_ulogic;
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cspr_tspr_ex5_is_mtspr : in std_ulogic;
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cspr_tspr_ex5_instr : in std_ulogic_vector(11 to 20);
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ex5_spr_wd : in std_ulogic_vector(64-regsize to 63);
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ex5_cia_p1 : in std_ulogic_vector(62-eff_ifar to 61);
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-- Decode Signals
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ex4_lr_update : in std_ulogic;
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ex4_ctr_dec_update : in std_ulogic;
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-- SPRs
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spr_iar : in std_ulogic_vector(62-eff_ifar to 61);
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spr_ctr : out std_ulogic_vector(0 to regsize-1);
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spr_lr : out std_ulogic_vector(0 to regsize-1);
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-- Power
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vdd : inout power_logic;
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gnd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_cpl_spr_tspr;
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architecture xuq_cpl_spr_tspr of xuq_cpl_spr_tspr is
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-- Types
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subtype DO is std_ulogic_vector(65-regsize to 64);
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-- SPR Registers
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signal ctr_d , ctr_q : std_ulogic_vector(64-(regsize) to 63);
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signal lr_d , lr_q : std_ulogic_vector(64-(regsize) to 63);
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-- FUNC Scanchain
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constant ctr_offset : natural := 0;
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constant lr_offset : natural := ctr_offset + ctr_q'length;
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constant last_reg_offset : natural := lr_offset + lr_q'length;
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-- BCFG Scanchain
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constant last_reg_offset_bcfg : natural := 1;
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-- CCFG Scanchain
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constant last_reg_offset_ccfg : natural := 1;
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-- DCFG Scanchain
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constant last_reg_offset_dcfg : natural := 1;
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-- Latches
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signal ex5_lr_update_q : std_ulogic; -- ex4_lr_update
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signal ex5_ctr_dec_update_q : std_ulogic; -- ex4_ctr_dec_update
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-- Scanchains
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constant ex5_lr_update_offset : integer := last_reg_offset;
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constant ex5_ctr_dec_update_offset : integer := ex5_lr_update_offset + 1;
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constant scan_right : integer := ex5_ctr_dec_update_offset + 1;
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signal siv : std_ulogic_vector(0 to scan_right-1);
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signal sov : std_ulogic_vector(0 to scan_right-1);
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-- Signals
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signal tiup : std_ulogic;
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signal tidn : std_ulogic_vector(00 to 63);
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signal ex2_instr : std_ulogic_vector(11 to 20);
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signal ex5_is_mtspr : std_ulogic;
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signal ex5_instr : std_ulogic_vector(11 to 20);
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signal ex5_lr_update : std_ulogic;
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signal ex5_ctr_dec_update : std_ulogic;
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signal spr_iar_int : std_ulogic_vector(0 to 62);
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-- Data
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signal ex5_ctr_di : std_ulogic_vector(ctr_q'range);
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signal ex5_lr_di : std_ulogic_vector(lr_q'range);
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signal
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ex2_ctr_rdec , ex2_iar_rdec , ex2_lr_rdec
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: std_ulogic;
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signal
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ex2_ctr_re , ex2_iar_re , ex2_lr_re
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: std_ulogic;
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signal
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ex5_ctr_wdec , ex5_iar_wdec , ex5_lr_wdec
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: std_ulogic;
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signal
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ex5_ctr_we , ex5_iar_we , ex5_lr_we
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: std_ulogic;
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signal
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ctr_act , iar_act , lr_act
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: std_ulogic;
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signal
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ctr_do , iar_do , lr_do
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: std_ulogic_vector(0 to 64);
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begin
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tiup <= '1';
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tidn <= (others=>'0');
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ex2_instr <= cspr_tspr_ex2_instr;
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ex5_is_mtspr <= cspr_tspr_ex5_is_mtspr;
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ex5_instr <= cspr_tspr_ex5_instr;
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ex5_lr_update <= ex5_val and ex5_lr_update_q;
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ex5_ctr_dec_update <= ex5_val and ex5_ctr_dec_update_q;
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spr_iar_int <= tidn(0 to 62-eff_ifar) & spr_iar;
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-- SPR Input Control
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-- CTR
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ctr_act <= ex5_ctr_we or ex5_ctr_dec_update;
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with ex5_ctr_dec_update_q select
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ctr_d <= std_ulogic_vector(unsigned(ctr_q) - 1) when '1',
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ex5_ctr_di when others;
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-- IAR
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iar_act <= tiup;
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-- LR
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lr_act <= ex5_lr_we or ex5_lr_update;
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with ex5_lr_update select
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lr_d <= ex5_cia_p1 & "00" when '1',
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ex5_lr_di when others;
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readmux_00 : if a2mode = 0 and hvmode = 0 generate
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tspr_cspr_ex2_tspr_rt <=
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(ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or
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(iar_do(DO'range) and (DO'range => ex2_iar_re )) or
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(lr_do(DO'range) and (DO'range => ex2_lr_re ));
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end generate;
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readmux_01 : if a2mode = 0 and hvmode = 1 generate
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tspr_cspr_ex2_tspr_rt <=
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(ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or
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(iar_do(DO'range) and (DO'range => ex2_iar_re )) or
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(lr_do(DO'range) and (DO'range => ex2_lr_re ));
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end generate;
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readmux_10 : if a2mode = 1 and hvmode = 0 generate
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tspr_cspr_ex2_tspr_rt <=
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(ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or
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(iar_do(DO'range) and (DO'range => ex2_iar_re )) or
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(lr_do(DO'range) and (DO'range => ex2_lr_re ));
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end generate;
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readmux_11 : if a2mode = 1 and hvmode = 1 generate
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tspr_cspr_ex2_tspr_rt <=
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(ctr_do(DO'range) and (DO'range => ex2_ctr_re )) or
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(iar_do(DO'range) and (DO'range => ex2_iar_re )) or
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(lr_do(DO'range) and (DO'range => ex2_lr_re ));
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end generate;
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ex2_ctr_rdec <= (ex2_instr(11 to 20) = "0100100000"); -- 9
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ex2_iar_rdec <= (ex2_instr(11 to 20) = "1001011011"); -- 882
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ex2_lr_rdec <= (ex2_instr(11 to 20) = "0100000000"); -- 8
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ex2_ctr_re <= ex2_ctr_rdec;
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ex2_iar_re <= ex2_iar_rdec;
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ex2_lr_re <= ex2_lr_rdec;
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ex5_ctr_wdec <= (ex5_instr(11 to 20) = "0100100000"); -- 9
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ex5_iar_wdec <= (ex5_instr(11 to 20) = "1001011011"); -- 882
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ex5_lr_wdec <= (ex5_instr(11 to 20) = "0100000000"); -- 8
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ex5_ctr_we <= ex5_val and ex5_is_mtspr and ex5_ctr_wdec;
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ex5_iar_we <= ex5_val and ex5_is_mtspr and ex5_iar_wdec;
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ex5_lr_we <= ex5_val and ex5_is_mtspr and ex5_lr_wdec;
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spr_ctr <= ctr_q(64-(regsize) to 63);
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spr_lr <= lr_q(64-(regsize) to 63);
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-- CTR
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ex5_ctr_di <= ex5_spr_wd(64-(regsize) to 63) ; --CTR
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ctr_do <= tidn(0 to 64-(regsize)) &
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ctr_q(64-(regsize) to 63) ; --CTR
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-- IAR
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iar_do <= tidn(0 to 0) &
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spr_iar_int(1 to 62) & --IAR
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tidn(62 to 63) ; --///
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-- LR
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ex5_lr_di <= ex5_spr_wd(64-(regsize) to 63) ; --LR
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lr_do <= tidn(0 to 64-(regsize)) &
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lr_q(64-(regsize) to 63) ; --LR
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-- Unused Signals
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mark_unused(ctr_do(0 to 64-regsize));
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mark_unused(iar_do(0 to 64-regsize));
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mark_unused(lr_do(0 to 64-regsize));
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ctr_latch : tri_ser_rlmreg_p
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generic map(width => ctr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map(nclk => nclk, vd => vdd, gd => gnd,
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act => ctr_act,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ctr_offset to ctr_offset + ctr_q'length-1),
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scout => sov(ctr_offset to ctr_offset + ctr_q'length-1),
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din => ctr_d,
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dout => ctr_q);
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lr_latch : tri_ser_rlmreg_p
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generic map(width => lr_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map(nclk => nclk, vd => vdd, gd => gnd,
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act => lr_act,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(lr_offset to lr_offset + lr_q'length-1),
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scout => sov(lr_offset to lr_offset + lr_q'length-1),
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din => lr_d,
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dout => lr_q);
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mark_unused(tidn(1 to 61));
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mark_unused(spr_iar_int(0));
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mark_unused(iar_act);
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mark_unused(ex5_iar_we);
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-- Latch Instances
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ex5_lr_update_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => tiup,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ex5_lr_update_offset),
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scout => sov(ex5_lr_update_offset),
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din => ex4_lr_update,
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dout => ex5_lr_update_q);
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ex5_ctr_dec_update_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => tiup,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ex5_ctr_dec_update_offset),
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scout => sov(ex5_ctr_dec_update_offset),
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din => ex4_ctr_dec_update,
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dout => ex5_ctr_dec_update_q);
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siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in;
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scan_out <= sov(0);
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end architecture xuq_cpl_spr_tspr;
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