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241 lines
13 KiB
VHDL
241 lines
13 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU Debug Event Muxing
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--
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library ieee,ibm,support,work,tri,clib;
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use ieee.std_logic_1164.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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entity xuq_debug is
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generic(
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expand_type : integer := 2);
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port(
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-- Clocks
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nclk : in clk_logic;
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-- Pervasive
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d_mode_dc : in std_ulogic;
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delay_lclkr_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic;
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mpw2_dc_b : in std_ulogic;
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sg_0 : in std_ulogic;
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func_slp_sl_thold_0_b : in std_ulogic;
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func_slp_sl_force : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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dec_byp_ex3_instr_trace_val : in std_ulogic;
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pc_xu_trace_bus_enable : in std_ulogic;
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debug_mux_ctrls : in std_ulogic_vector(0 to 15);
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trigger_data_in : in std_ulogic_vector(0 to 11);
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debug_data_in : in std_ulogic_vector(0 to 87);
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trigger_data_out : out std_ulogic_vector(0 to 11);
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debug_data_out : out std_ulogic_vector(0 to 87);
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dbg_group0 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group1 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group2 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group3 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group4 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group5 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group6 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group7 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group8 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group9 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group10 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group11 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group12 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group13 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group14 : in std_ulogic_vector(0 to 87) := (others=>'0');
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dbg_group15 : in std_ulogic_vector(0 to 87) := (others=>'0');
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trg_group0 : in std_ulogic_vector(0 to 11) := (others=>'0');
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trg_group1 : in std_ulogic_vector(0 to 11) := (others=>'0');
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trg_group2 : in std_ulogic_vector(0 to 11) := (others=>'0');
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trg_group3 : in std_ulogic_vector(0 to 11) := (others=>'0');
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-- Power
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vdd : inout power_logic;
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gnd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_debug;
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architecture xuq_debug of xuq_debug is
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signal tiup : std_ulogic;
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-- Latches
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signal trace_bus_enable_q : std_ulogic; -- input=>pc_xu_trace_bus_enable, sleep=>Y, needs_sreset=>0
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signal debug_mux_ctrls_q : std_ulogic_vector(0 to 15); -- input=>debug_mux_ctrls, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0
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signal debug_mux_ctrls_int_q, debug_mux_ctrls_int : std_ulogic_vector(0 to 15); -- input=>debug_mux_ctrls_int, act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0
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signal trigger_data_out_q, trigger_data_out_d : std_ulogic_vector(0 to 11); -- act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0
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signal debug_data_out_q, debug_data_out_d : std_ulogic_vector(0 to 87); -- act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0
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signal ex4_instr_trace_val_q : std_ulogic; -- input=>dec_byp_ex3_instr_trace_val,act=>trace_bus_enable_q, sleep=>Y, needs_sreset=>0
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-- Scanrings
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constant trace_bus_enable_offset : integer := 0;
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constant debug_mux_ctrls_offset : integer := trace_bus_enable_offset + 1;
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constant debug_mux_ctrls_int_offset : integer := debug_mux_ctrls_offset + debug_mux_ctrls_q'length;
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constant trigger_data_out_offset : integer := debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length;
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constant debug_data_out_offset : integer := trigger_data_out_offset + trigger_data_out_q'length;
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constant ex4_instr_trace_val_offset : integer := debug_data_out_offset + debug_data_out_q'length;
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constant scan_right : integer := ex4_instr_trace_val_offset + 1;
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signal siv : std_ulogic_vector(0 to scan_right-1);
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signal sov : std_ulogic_vector(0 to scan_right-1);
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begin
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tiup <= '1';
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trigger_data_out <= trigger_data_out_q;
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debug_data_out <= debug_data_out_q;
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with ex4_instr_trace_val_q select
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debug_mux_ctrls_int <= x"11E0" when '1',
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debug_mux_ctrls_q when others;
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xu_debug_mux : entity clib.c_debug_mux16(c_debug_mux16)
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port map(
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vd => vdd,
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gd => gnd,
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select_bits => debug_mux_ctrls_int_q,
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trace_data_in => debug_data_in,
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trigger_data_in => trigger_data_in,
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dbg_group0 => dbg_group0,
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dbg_group1 => dbg_group1,
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dbg_group2 => dbg_group2,
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dbg_group3 => dbg_group3,
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dbg_group4 => dbg_group4,
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dbg_group5 => dbg_group5,
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dbg_group6 => dbg_group6,
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dbg_group7 => dbg_group7,
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dbg_group8 => dbg_group8,
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dbg_group9 => dbg_group9,
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dbg_group10 => dbg_group10,
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dbg_group11 => dbg_group11,
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dbg_group12 => dbg_group12,
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dbg_group13 => dbg_group13,
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dbg_group14 => dbg_group14,
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dbg_group15 => dbg_group15,
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trg_group0 => trg_group0,
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trg_group1 => trg_group1,
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trg_group2 => trg_group2,
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trg_group3 => trg_group3,
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trigger_data_out => trigger_data_out_d,
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trace_data_out => debug_data_out_d);
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-- Latches
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trace_bus_enable_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => tiup,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(trace_bus_enable_offset),
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scout => sov(trace_bus_enable_offset),
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din => pc_xu_trace_bus_enable,
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dout => trace_bus_enable_q);
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debug_mux_ctrls_latch : tri_rlmreg_p
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generic map (width => debug_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => trace_bus_enable_q,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1),
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scout => sov(debug_mux_ctrls_offset to debug_mux_ctrls_offset + debug_mux_ctrls_q'length-1),
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din => debug_mux_ctrls,
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dout => debug_mux_ctrls_q);
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debug_mux_ctrls_int_latch : tri_rlmreg_p
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generic map (width => debug_mux_ctrls_int_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => trace_bus_enable_q,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1),
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scout => sov(debug_mux_ctrls_int_offset to debug_mux_ctrls_int_offset + debug_mux_ctrls_int_q'length-1),
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din => debug_mux_ctrls_int,
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dout => debug_mux_ctrls_int_q);
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trigger_data_out_latch : tri_rlmreg_p
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generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => trace_bus_enable_q,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1),
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scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1),
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din => trigger_data_out_d,
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dout => trigger_data_out_q);
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debug_data_out_latch : tri_rlmreg_p
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generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => trace_bus_enable_q,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1),
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scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1),
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din => debug_data_out_d,
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dout => debug_data_out_q);
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ex4_instr_trace_val_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => trace_bus_enable_q,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ex4_instr_trace_val_offset),
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scout => sov(ex4_instr_trace_val_offset),
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din => dec_byp_ex3_instr_trace_val,
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dout => ex4_instr_trace_val_q);
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siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in;
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scan_out <= sov(0);
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end architecture xuq_debug;
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