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371 lines
20 KiB
VHDL
371 lines
20 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: LSU Debug Event Muxing
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--
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library ieee,ibm,support,work,tri,work;
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use ieee.std_logic_1164.all;
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use support.power_logic_pkg.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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use tri.tri_latches_pkg.all;
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use work.xuq_pkg.all;
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entity xuq_debug_mux32 is
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generic(expand_type :integer := 2);
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port(
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-- PC Debug Control
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trace_bus_enable :in std_ulogic;
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trace_unit_sel :in std_ulogic_vector(0 to 15);
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-- Pass Thru Debug Trace Bus
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debug_data_in :in std_ulogic_vector(0 to 87);
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trigger_data_in :in std_ulogic_vector(0 to 11);
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-- Debug Data In
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dbg_group0 :in std_ulogic_vector(0 to 87);
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dbg_group1 :in std_ulogic_vector(0 to 87);
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dbg_group2 :in std_ulogic_vector(0 to 87);
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dbg_group3 :in std_ulogic_vector(0 to 87);
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dbg_group4 :in std_ulogic_vector(0 to 87);
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dbg_group5 :in std_ulogic_vector(0 to 87);
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dbg_group6 :in std_ulogic_vector(0 to 87);
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dbg_group7 :in std_ulogic_vector(0 to 87);
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dbg_group8 :in std_ulogic_vector(0 to 87);
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dbg_group9 :in std_ulogic_vector(0 to 87);
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dbg_group10 :in std_ulogic_vector(0 to 87);
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dbg_group11 :in std_ulogic_vector(0 to 87);
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dbg_group12 :in std_ulogic_vector(0 to 87);
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dbg_group13 :in std_ulogic_vector(0 to 87);
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dbg_group14 :in std_ulogic_vector(0 to 87);
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dbg_group15 :in std_ulogic_vector(0 to 87);
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dbg_group16 :in std_ulogic_vector(0 to 87);
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dbg_group17 :in std_ulogic_vector(0 to 87);
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dbg_group18 :in std_ulogic_vector(0 to 87);
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dbg_group19 :in std_ulogic_vector(0 to 87);
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dbg_group20 :in std_ulogic_vector(0 to 87);
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dbg_group21 :in std_ulogic_vector(0 to 87);
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dbg_group22 :in std_ulogic_vector(0 to 87);
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dbg_group23 :in std_ulogic_vector(0 to 87);
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dbg_group24 :in std_ulogic_vector(0 to 87);
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dbg_group25 :in std_ulogic_vector(0 to 87);
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dbg_group26 :in std_ulogic_vector(0 to 87);
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dbg_group27 :in std_ulogic_vector(0 to 87);
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dbg_group28 :in std_ulogic_vector(0 to 87);
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dbg_group29 :in std_ulogic_vector(0 to 87);
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dbg_group30 :in std_ulogic_vector(0 to 87);
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dbg_group31 :in std_ulogic_vector(0 to 87);
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-- Trigger Data In
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trg_group0 :in std_ulogic_vector(0 to 11);
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trg_group1 :in std_ulogic_vector(0 to 11);
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trg_group2 :in std_ulogic_vector(0 to 11);
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trg_group3 :in std_ulogic_vector(0 to 11);
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-- Outputs
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trigger_data_out :out std_ulogic_vector(0 to 11);
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debug_data_out :out std_ulogic_vector(0 to 87);
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-- Power
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vdd :inout power_logic;
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gnd :inout power_logic;
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nclk :in clk_logic;
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sg_0 :in std_ulogic;
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func_slp_sl_thold_0_b :in std_ulogic;
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func_slp_sl_force :in std_ulogic;
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d_mode_dc :in std_ulogic;
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delay_lclkr_dc :in std_ulogic;
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mpw1_dc_b :in std_ulogic;
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mpw2_dc_b :in std_ulogic;
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scan_in :in std_ulogic;
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scan_out :out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_debug_mux32;
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architecture xuq_debug_mux32 of xuq_debug_mux32 is
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type ARY_32 is array (0 to 31) of std_ulogic_vector(0 to 3);
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signal dbg_group_int_data :std_ulogic_vector(0 to 87);
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signal dbg_group_rotate0 :std_ulogic_vector(0 to 87);
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signal dbg_group_rotate1 :std_ulogic_vector(0 to 87);
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signal dbg_group_rotate2 :std_ulogic_vector(0 to 87);
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signal dbg_group_rotate3 :std_ulogic_vector(0 to 87);
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signal dbg_group_rotate :std_ulogic_vector(0 to 87);
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signal dbg_group_pthru_data0 :std_ulogic_vector(0 to 21);
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signal dbg_group_pthru_data1 :std_ulogic_vector(0 to 21);
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signal dbg_group_pthru_data2 :std_ulogic_vector(0 to 21);
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signal dbg_group_pthru_data3 :std_ulogic_vector(0 to 21);
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signal dbg_group_pthru_data :std_ulogic_vector(0 to 87);
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signal debug_data_out_d :std_ulogic_vector(0 to 87);
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signal debug_data_out_q :std_ulogic_vector(0 to 87);
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signal dbg_group_int_trig :std_ulogic_vector(0 to 11);
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signal dbg_group_rot_trig0 :std_ulogic_vector(0 to 11);
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signal dbg_group_rot_trig1 :std_ulogic_vector(0 to 11);
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signal dbg_group_rot_trig :std_ulogic_vector(0 to 11);
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signal dbg_group_pthru_trig0 :std_ulogic_vector(0 to 5);
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signal dbg_group_pthru_trig1 :std_ulogic_vector(0 to 5);
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signal dbg_group_pthru_trig :std_ulogic_vector(0 to 11);
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signal trigger_data_out_d :std_ulogic_vector(0 to 11);
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signal trigger_data_out_q :std_ulogic_vector(0 to 11);
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signal trace_unit_sel10 :std_ulogic_vector(0 to 31);
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signal trace_unit_selC840 :std_ulogic_vector(0 to 31);
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signal trace_unit_sel3210 :std_ulogic_vector(0 to 31);
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signal dbg_data_unit_sel_d :ARY_32;
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signal dbg_data_unit_sel_q :ARY_32;
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signal dbg_trace_unit_sel_d :std_ulogic_vector(32 to 46);
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signal dbg_trace_unit_sel_q :std_ulogic_vector(32 to 46);
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signal dbg_rot_grp_sel :std_ulogic_vector(0 to 3);
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signal dbg_data_pthru_sel :std_ulogic_vector(0 to 3);
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signal dbg_trig_grp_sel :std_ulogic_vector(0 to 3);
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signal dbg_rot_trig_sel :std_ulogic;
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signal dbg_trig_pthru_sel :std_ulogic_vector(0 to 1);
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constant dbg_data_unit_sel_offset :natural := 0;
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constant dbg_trace_unit_sel_offset :natural := dbg_data_unit_sel_offset + dbg_data_unit_sel_q(0)'length*32;
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constant trigger_data_out_offset :natural := dbg_trace_unit_sel_offset + 15;
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constant debug_data_out_offset :natural := trigger_data_out_offset + 12;
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constant scan_right :natural := debug_data_out_offset + 88 - 1;
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signal siv :std_ulogic_vector(0 to scan_right);
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signal sov :std_ulogic_vector(0 to scan_right);
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begin
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- MUX Control Generation
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Generate 1-hot Debug Data Group Select
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with trace_unit_sel(0) select
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trace_unit_sel10 <= x"80000000" when '0',
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x"00008000" when others;
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with trace_unit_sel(1 to 2) select
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trace_unit_selC840 <= trace_unit_sel10(0 to 31) when "00",
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x"0" & trace_unit_sel10(0 to 27) when "01",
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x"00" & trace_unit_sel10(0 to 23) when "10",
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x"000" & trace_unit_sel10(0 to 19) when others;
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with trace_unit_sel(3 to 4) select
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trace_unit_sel3210 <= trace_unit_selC840(0 to 31) when "00",
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'0' & trace_unit_selC840(0 to 30) when "01",
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"00" & trace_unit_selC840(0 to 29) when "10",
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"000" & trace_unit_selC840(0 to 28) when others;
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-- Generate 1-hot Debug Data Group Rotate
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with trace_unit_sel(5 to 6) select
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dbg_trace_unit_sel_d(32 to 35) <= "1000" when "00",
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"0100" when "01",
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"0010" when "10",
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"0001" when others;
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-- Debug Data Pass Through
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dbg_trace_unit_sel_d(36 to 39) <= trace_unit_sel(7 to 10);
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-- Generate 1-hot Trigger Group Select
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with trace_unit_sel(11 to 12) select
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dbg_trace_unit_sel_d(40 to 43) <= "1000" when "00",
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"0100" when "01",
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"0010" when "10",
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"0001" when others;
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-- Generate 1-hot Trigger Group Rotate
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dbg_trace_unit_sel_d(44) <= trace_unit_sel(13);
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-- Trigger Pass Through
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dbg_trace_unit_sel_d(45 to 46) <= trace_unit_sel(14 to 15);
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dbg_rot_grp_sel <= dbg_trace_unit_sel_q(32 to 35);
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dbg_data_pthru_sel <= dbg_trace_unit_sel_q(36 to 39);
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dbg_trig_grp_sel <= dbg_trace_unit_sel_q(40 to 43);
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dbg_rot_trig_sel <= dbg_trace_unit_sel_q(44);
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dbg_trig_pthru_sel <= dbg_trace_unit_sel_q(45 to 46);
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Debug Muxing
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Select Internal Debug Group
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dbg_group_int_data <= (dbg_group0 and fanout(dbg_data_unit_sel_q(00),88)) or
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(dbg_group1 and fanout(dbg_data_unit_sel_q(01),88)) or
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(dbg_group2 and fanout(dbg_data_unit_sel_q(02),88)) or
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(dbg_group3 and fanout(dbg_data_unit_sel_q(03),88)) or
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(dbg_group4 and fanout(dbg_data_unit_sel_q(04),88)) or
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(dbg_group5 and fanout(dbg_data_unit_sel_q(05),88)) or
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(dbg_group6 and fanout(dbg_data_unit_sel_q(06),88)) or
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(dbg_group7 and fanout(dbg_data_unit_sel_q(07),88)) or
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(dbg_group8 and fanout(dbg_data_unit_sel_q(08),88)) or
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(dbg_group9 and fanout(dbg_data_unit_sel_q(09),88)) or
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(dbg_group10 and fanout(dbg_data_unit_sel_q(10),88)) or
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(dbg_group11 and fanout(dbg_data_unit_sel_q(11),88)) or
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(dbg_group12 and fanout(dbg_data_unit_sel_q(12),88)) or
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(dbg_group13 and fanout(dbg_data_unit_sel_q(13),88)) or
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(dbg_group14 and fanout(dbg_data_unit_sel_q(14),88)) or
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(dbg_group15 and fanout(dbg_data_unit_sel_q(15),88)) or
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(dbg_group16 and fanout(dbg_data_unit_sel_q(16),88)) or
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(dbg_group17 and fanout(dbg_data_unit_sel_q(17),88)) or
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(dbg_group18 and fanout(dbg_data_unit_sel_q(18),88)) or
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(dbg_group19 and fanout(dbg_data_unit_sel_q(19),88)) or
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(dbg_group20 and fanout(dbg_data_unit_sel_q(20),88)) or
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(dbg_group21 and fanout(dbg_data_unit_sel_q(21),88)) or
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(dbg_group22 and fanout(dbg_data_unit_sel_q(22),88)) or
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(dbg_group23 and fanout(dbg_data_unit_sel_q(23),88)) or
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(dbg_group24 and fanout(dbg_data_unit_sel_q(24),88)) or
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(dbg_group25 and fanout(dbg_data_unit_sel_q(25),88)) or
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(dbg_group26 and fanout(dbg_data_unit_sel_q(26),88)) or
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(dbg_group27 and fanout(dbg_data_unit_sel_q(27),88)) or
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(dbg_group28 and fanout(dbg_data_unit_sel_q(28),88)) or
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(dbg_group29 and fanout(dbg_data_unit_sel_q(29),88)) or
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(dbg_group30 and fanout(dbg_data_unit_sel_q(30),88)) or
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(dbg_group31 and fanout(dbg_data_unit_sel_q(31),88));
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-- Rotate Internal Debug Group
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dbg_group_rotate0 <= dbg_group_int_data(0 to 87);
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dbg_group_rotate1 <= dbg_group_int_data(66 to 87) & dbg_group_int_data(0 to 65);
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dbg_group_rotate2 <= dbg_group_int_data(44 to 87) & dbg_group_int_data(0 to 43);
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dbg_group_rotate3 <= dbg_group_int_data(22 to 87) & dbg_group_int_data(0 to 21);
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dbg_group_rotate <= gate(dbg_group_rotate0, dbg_rot_grp_sel(0)) or gate(dbg_group_rotate1, dbg_rot_grp_sel(1)) or
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gate(dbg_group_rotate2, dbg_rot_grp_sel(2)) or gate(dbg_group_rotate3, dbg_rot_grp_sel(3));
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-- Pass Thru Debug Select
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dbg_group_pthru_data0 <= gate(dbg_group_rotate(0 to 21), dbg_data_pthru_sel(0)) or gate(debug_data_in(0 to 21), not dbg_data_pthru_sel(0));
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dbg_group_pthru_data1 <= gate(dbg_group_rotate(22 to 43), dbg_data_pthru_sel(1)) or gate(debug_data_in(22 to 43), not dbg_data_pthru_sel(1));
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dbg_group_pthru_data2 <= gate(dbg_group_rotate(44 to 65), dbg_data_pthru_sel(2)) or gate(debug_data_in(44 to 65), not dbg_data_pthru_sel(2));
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dbg_group_pthru_data3 <= gate(dbg_group_rotate(66 to 87), dbg_data_pthru_sel(3)) or gate(debug_data_in(66 to 87), not dbg_data_pthru_sel(3));
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dbg_group_pthru_data <= dbg_group_pthru_data0 & dbg_group_pthru_data1 & dbg_group_pthru_data2 & dbg_group_pthru_data3;
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debug_data_out_d <= dbg_group_pthru_data;
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-- Select Internal Trigger Group
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dbg_group_int_trig <= gate(trg_group0, dbg_trig_grp_sel(0)) or gate(trg_group1, dbg_trig_grp_sel(1)) or gate(trg_group2, dbg_trig_grp_sel(2)) or gate(trg_group3, dbg_trig_grp_sel(3));
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-- Rotate Internal Trigger Group
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dbg_group_rot_trig0 <= dbg_group_int_trig(0 to 11);
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dbg_group_rot_trig1 <= dbg_group_int_trig(6 to 11) & dbg_group_int_trig(0 to 5);
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dbg_group_rot_trig <= gate(dbg_group_rot_trig0, not dbg_rot_trig_sel) or gate(dbg_group_rot_trig1, dbg_rot_trig_sel);
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-- Pass Thru Trigger Select
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dbg_group_pthru_trig0 <= gate(dbg_group_rot_trig(0 to 5), dbg_trig_pthru_sel(0)) or gate(trigger_data_in(0 to 5), not dbg_trig_pthru_sel(0));
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dbg_group_pthru_trig1 <= gate(dbg_group_rot_trig(6 to 11), dbg_trig_pthru_sel(1)) or gate(trigger_data_in(6 to 11), not dbg_trig_pthru_sel(1));
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dbg_group_pthru_trig <= dbg_group_pthru_trig0 & dbg_group_pthru_trig1;
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trigger_data_out_d <= dbg_group_pthru_trig;
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Outputs
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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debug_data_out <= debug_data_out_q;
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trigger_data_out <= trigger_data_out_q;
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Latches
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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dbg_data_unit_sel_gen : for g in 0 to 31 generate
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dbg_data_unit_sel_latch : tri_rlmreg_p
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generic map (width => dbg_data_unit_sel_q(g)'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => trace_bus_enable,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(dbg_data_unit_sel_offset+dbg_data_unit_sel_q(g)'length*g to dbg_data_unit_sel_offset + dbg_data_unit_sel_q(g)'length*(g+1)-1),
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scout => sov(dbg_data_unit_sel_offset+dbg_data_unit_sel_q(g)'length*g to dbg_data_unit_sel_offset + dbg_data_unit_sel_q(g)'length*(g+1)-1),
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din => dbg_data_unit_sel_d(g),
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dout => dbg_data_unit_sel_q(g));
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dbg_data_unit_sel_d(g) <= (others=>trace_unit_sel3210(g));
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end generate;
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dbg_trace_unit_sel_latch : tri_rlmreg_p
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generic map (width => dbg_trace_unit_sel_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => trace_bus_enable,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(dbg_trace_unit_sel_offset to dbg_trace_unit_sel_offset + dbg_trace_unit_sel_q'length-1),
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scout => sov(dbg_trace_unit_sel_offset to dbg_trace_unit_sel_offset + dbg_trace_unit_sel_q'length-1),
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din => dbg_trace_unit_sel_d,
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dout => dbg_trace_unit_sel_q);
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trigger_data_out_latch : tri_rlmreg_p
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generic map (width => trigger_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => trace_bus_enable,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1),
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scout => sov(trigger_data_out_offset to trigger_data_out_offset + trigger_data_out_q'length-1),
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din => trigger_data_out_d,
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dout => trigger_data_out_q);
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debug_data_out_latch : tri_rlmreg_p
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generic map (width => debug_data_out_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => trace_bus_enable,
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forcee => func_slp_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_slp_sl_thold_0_b,
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sg => sg_0,
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scin => siv(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1),
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scout => sov(debug_data_out_offset to debug_data_out_offset + debug_data_out_q'length-1),
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din => debug_data_out_d,
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dout => debug_data_out_q);
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siv(0 to scan_right) <= sov(1 to scan_right) & scan_in;
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scan_out <= sov(0);
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end architecture xuq_debug_mux32;
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