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493 lines
24 KiB
VHDL
493 lines
24 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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LIBRARY work ;
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LIBRARY ieee; USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY ibm;
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USE ibm.std_ulogic_support.all;
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USE ibm.std_ulogic_unsigned.all;
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USE ibm.std_ulogic_function_support.all;
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LIBRARY support;
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USE support.power_logic_pkg.all;
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LIBRARY tri; USE tri.tri_latches_pkg.all;
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LIBRARY work; USE work.xuq_pkg.all;
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entity xuq_dec_dcdmrg is
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port (
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i : in std_ulogic_vector(0 to 31);
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dec_alu_rf1_sel_rot_log : out std_ulogic;
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dec_alu_rf1_sh_right : out std_ulogic;
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dec_alu_rf1_sh_word : out std_ulogic;
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dec_alu_rf1_sgnxtd_byte : out std_ulogic;
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dec_alu_rf1_sgnxtd_half : out std_ulogic;
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dec_alu_rf1_sgnxtd_wd : out std_ulogic;
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dec_alu_rf1_sra_dw : out std_ulogic;
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dec_alu_rf1_sra_wd : out std_ulogic;
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dec_alu_rf1_chk_shov_dw : out std_ulogic;
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dec_alu_rf1_chk_shov_wd : out std_ulogic;
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dec_alu_rf1_use_me_ins_hi : out std_ulogic;
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dec_alu_rf1_use_me_ins_lo : out std_ulogic;
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dec_alu_rf1_use_mb_ins_hi : out std_ulogic;
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dec_alu_rf1_use_mb_ins_lo : out std_ulogic;
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dec_alu_rf1_use_me_rb_hi : out std_ulogic;
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dec_alu_rf1_use_me_rb_lo : out std_ulogic;
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dec_alu_rf1_use_mb_rb_hi : out std_ulogic;
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dec_alu_rf1_use_mb_rb_lo : out std_ulogic;
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dec_alu_rf1_use_rb_amt_hi : out std_ulogic;
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dec_alu_rf1_use_rb_amt_lo : out std_ulogic;
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dec_alu_rf1_zm_ins : out std_ulogic;
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dec_alu_rf1_cr_logical : out std_ulogic;
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dec_alu_rf1_cr_log_fcn : out std_ulogic_vector(0 to 3);
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dec_alu_rf1_log_fcn : out std_ulogic_vector(0 to 3);
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dec_alu_rf1_me_ins_b : out std_ulogic_vector(0 to 5);
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dec_alu_rf1_mb_ins : out std_ulogic_vector(0 to 5);
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dec_alu_rf1_sh_amt : out std_ulogic_vector(0 to 5);
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dec_alu_rf1_mb_gt_me : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_dec_dcdmrg;
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architecture xuq_dec_dcdmrg of xuq_dec_dcdmrg is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal cmp_byt : std_ulogic;
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signal cr_log : std_ulogic;
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signal rotlw : std_ulogic;
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signal imm_log : std_ulogic;
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signal rotld : std_ulogic;
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signal x31 : std_ulogic;
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signal f0_xxxx00 : std_ulogic;
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signal f0_xxx0xx : std_ulogic;
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signal f0_xxxx0x : std_ulogic;
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signal f1_1xxxx : std_ulogic;
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signal f1_111xx : std_ulogic;
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signal f1_110xx : std_ulogic;
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signal f1_x1x1x : std_ulogic;
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signal f1_x1xx0 : std_ulogic;
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signal f1_x1xx1 : std_ulogic;
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signal f1_xxx00 : std_ulogic;
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signal f1_xxx11 : std_ulogic;
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signal f1_xx10x : std_ulogic;
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signal f2_11xxx : std_ulogic;
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signal f2_xxx0x : std_ulogic;
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signal f2_111xx : std_ulogic;
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signal f1_xxx01 : std_ulogic;
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signal f1_xxx10 : std_ulogic;
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signal f2_xx01x : std_ulogic;
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signal f2_xx00x : std_ulogic;
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signal rotlw_nm : std_ulogic;
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signal rotlw_pass : std_ulogic;
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signal rotld_pass : std_ulogic;
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signal sh_lft_rb : std_ulogic;
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signal sh_lft_rb_dw : std_ulogic;
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signal sh_rgt : std_ulogic;
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signal sh_rgt_rb : std_ulogic;
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signal sh_rgt_rb_dw : std_ulogic;
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signal shift_imm : std_ulogic;
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signal sh_rb : std_ulogic;
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signal sh_rb_dw : std_ulogic;
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signal sh_rb_wd : std_ulogic;
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signal x31_sh_log_sgn : std_ulogic;
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signal op_sgn_xtd : std_ulogic;
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signal op_sra : std_ulogic;
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signal wd_if_sh : std_ulogic;
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signal xtd_log : std_ulogic;
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signal sh_word_int : std_ulogic;
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signal imm_xor_or : std_ulogic;
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signal imm_and_or : std_ulogic;
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signal xtd_nor : std_ulogic;
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signal xtd_eqv_orc_nand : std_ulogic;
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signal xtd_nand : std_ulogic;
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signal xtd_andc_xor_or : std_ulogic;
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signal xtd_and_eqv_orc : std_ulogic;
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signal xtd_or_orc : std_ulogic;
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signal xtd_xor_or : std_ulogic;
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signal sel_ins_amt_hi : std_ulogic;
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signal sel_ins_me_lo_wd : std_ulogic;
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signal sel_ins_me_lo_dw : std_ulogic;
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signal sel_ins_amt_lo : std_ulogic;
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signal sel_ins_me_hi : std_ulogic;
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signal rot_imm_mb : std_ulogic;
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signal gt5_g_45 : std_ulogic;
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signal gt5_g_23 : std_ulogic;
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signal gt5_g_1 : std_ulogic;
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signal gt5_t_23 : std_ulogic;
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signal gt5_t_1 : std_ulogic;
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signal mb_gt_me_cmp_wd0_b : std_ulogic;
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signal mb_gt_me_cmp_wd1_b : std_ulogic;
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signal mb_gt_me_cmp_wd2_b : std_ulogic;
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signal mb_gt_me_cmp_wd : std_ulogic;
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signal gt6_g_45 : std_ulogic;
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signal gt6_g_23 : std_ulogic;
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signal gt6_g_01 : std_ulogic;
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signal gt6_t_23 : std_ulogic;
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signal gt6_t_01 : std_ulogic;
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signal mb_gt_me_cmp_dw0_b : std_ulogic;
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signal mb_gt_me_cmp_dw1_b : std_ulogic;
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signal mb_gt_me_cmp_dw2_b : std_ulogic;
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signal mb_gt_me_cmp_dw : std_ulogic;
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signal me_ins : std_ulogic_vector(0 to 5);
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signal gt5_in0 : std_ulogic_vector(1 to 5);
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signal gt5_in1 : std_ulogic_vector(1 to 5);
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signal gt6_in0 : std_ulogic_vector(0 to 5);
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signal gt6_in1 : std_ulogic_vector(0 to 5);
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signal gt5_g_b : std_ulogic_vector(1 to 5);
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signal gt5_t_b : std_ulogic_vector(1 to 4);
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signal gt6_g_b : std_ulogic_vector(0 to 5);
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signal gt6_t_b : std_ulogic_vector(0 to 4);
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signal f0_xxxx11 : std_ulogic;
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signal f1_0xxxx : std_ulogic;
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signal f1_1xxx0 : std_ulogic;
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signal f1_xxxx0 : std_ulogic;
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signal f1_xxxx1 : std_ulogic;
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signal f2_xxx1x : std_ulogic;
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signal f1_xx1xx : std_ulogic;
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signal xtd_nand_or_orc : std_ulogic;
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signal rld_cr : std_ulogic;
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signal rld_cl : std_ulogic;
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signal rld_icr : std_ulogic;
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signal rld_icl : std_ulogic;
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signal rld_ic : std_ulogic;
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signal rld_imi : std_ulogic;
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signal sh_lft_imm_dw : std_ulogic;
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signal sh_lft_imm : std_ulogic;
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signal sh_rgt_imm_dw : std_ulogic;
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signal sh_rgt_imm : std_ulogic;
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signal rotld_en_mbgtme : std_ulogic;
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signal rf1_log_fcn : std_ulogic_vector(0 to 3);
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signal isel : std_ulogic;
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begin
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----------------------------------------------------
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-- decode primary field opcode bits [0:5] ---
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----------------------------------------------------
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isel <= '1' when x31='1' and i(26 to 30) = "01111" else '0';
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cmp_byt <= '1' when x31='1' and i(21 to 30) = "0111111100" else '0'; -- 31/508
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cr_log <= not i(0) and i(1) and not i(2) and not i(3) and i(4) and i(5) ; --010011 (19)
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rotlw <= not i(0) and i(1) and not i(2) and i(3) ; --0101xx (20:23)
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imm_log <= not i(0) and i(1) and i(2) and (not i(3) or not i(4) ); --0110xx (24:27)
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--01110x (28,29)
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rotld <= not i(0) and i(1) and i(2) and i(3) and i(4) and not i(5) ; --011110 (30)
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x31 <= not i(0) and i(1) and i(2) and i(3) and i(4) and i(5) ; --011111 (31)
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f0_xxxx00 <= not i(4) and not i(5) ;
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f0_xxx0xx <= not i(3) ;
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f0_xxxx0x <= not i(4) ;
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f0_xxxx11 <= i(4) and i(5) ;
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-----------------------------------------------------
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-- decode i(21:25)
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-----------------------------------------------------
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f1_0xxxx <= not i(21) ;
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f1_110xx <= i(21) and i(22) and not i(23) ;
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f1_111xx <= i(21) and i(22) and i(23) ;
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f1_1xxx0 <= i(21) and not i(25) ;
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f1_1xxxx <= i(21) ;
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f1_x1x1x <= i(22) and i(24) ;
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f1_xx1xx <= i(23) ;
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f1_x1xx0 <= i(22) and not i(25) ;
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f1_x1xx1 <= i(22) and i(25) ;
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f1_xx10x <= i(23) and not i(24) ;
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f1_xxx01 <= not i(24) and i(25) ;
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f1_xxx11 <= i(24) and i(25) ;
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f1_xxxx0 <= not i(25) ;
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f1_xxxx1 <= i(25) ;
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f1_xxx00 <= not i(24) and not i(25) ;
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f1_xxx10 <= i(24) and not i(25) ;
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-----------------------------------------------------
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-- decode i(26:30)
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-----------------------------------------------------
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f2_11xxx <= i(26) and i(27) ; -- shifts / logicals / sign_xtd
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f2_xxx0x <= not i(29) ; -- word / double
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f2_111xx <= i(26) and i(27) and i(28) ;
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f2_xx01x <= not i(28) and i(29) ;
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f2_xx00x <= not i(28) and not i(29) ;
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f2_xxx1x <= i(29) ;
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rotlw_nm <= rotlw and f0_xxxx11 ;
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rotlw_pass <= rotlw and f0_xxxx00 ;
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rotld_pass <= rld_imi ;
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sh_lft_rb <= x31 and f1_0xxxx ;
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sh_lft_rb_dw <= x31 and f1_0xxxx and f2_xxx1x ;
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sh_rgt <= x31 and f1_1xxxx ;
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sh_rgt_rb <= x31 and f1_1xxx0 ;
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sh_rgt_rb_dw <= x31 and f1_1xxx0 and f2_xxx1x ;
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shift_imm <= x31 and f1_xxxx1 ;
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sh_rb <= x31 and f1_xxxx0 ;
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sh_rb_dw <= x31 and f1_xxxx0 and f2_xxx1x ;
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sh_rb_wd <= x31 and f1_xxxx0 and f2_xxx0x ;
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x31_sh_log_sgn <= x31 and f2_11xxx ;
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op_sgn_xtd <= x31 and f1_111xx ;
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op_sra <= x31 and f1_110xx ;
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wd_if_sh <= x31 and f2_xxx0x ;
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xtd_log <= x31 and f2_111xx ;
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sh_lft_imm_dw <= tidn;
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sh_lft_imm <= tidn;
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sh_rgt_imm_dw <= x31 and i(21) and i(25) and i(29) ;
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sh_rgt_imm <= x31 and i(21) and i(25) ;
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-----------------------------------------------------
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-- output signal
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-----------------------------------------------------
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-- (select to rot/log result instead of the adder result)
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dec_alu_rf1_sel_rot_log <= (cmp_byt ) or
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(cr_log ) or
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(rotlw ) or
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(imm_log ) or
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(rotld ) or
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(x31_sh_log_sgn );
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-- (zero out the mask to pass "insert_data" as the result)
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dec_alu_rf1_zm_ins <= (isel ) or
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(cmp_byt ) or
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(cr_log ) or
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(xtd_log ) or
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(imm_log ) or
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(op_sgn_xtd ); -- sgn extends
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-- (only needs to be correct when shifting)
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dec_alu_rf1_sh_right <= sh_rgt;
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sh_word_int <=(rotlw ) or
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(wd_if_sh );
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-- (only needs to be correct when shifting)
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dec_alu_rf1_sh_word <= sh_word_int ;
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dec_alu_rf1_cr_logical <= cr_log ;
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dec_alu_rf1_sgnxtd_byte <= op_sgn_xtd and f1_xxx01 and not isel;
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dec_alu_rf1_sgnxtd_half <= op_sgn_xtd and f1_xxx00 and not isel;
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dec_alu_rf1_sgnxtd_wd <= op_sgn_xtd and f1_xxx10 and not isel;
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dec_alu_rf1_sra_dw <= op_sra and f2_xx01x and not isel;
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dec_alu_rf1_sra_wd <= op_sra and f2_xx00x and not isel;
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dec_alu_rf1_cr_log_fcn(0) <= i(25) ;
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dec_alu_rf1_cr_log_fcn(1) <= i(24) ;
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dec_alu_rf1_cr_log_fcn(2) <= i(23) ;
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dec_alu_rf1_cr_log_fcn(3) <= i(22) ;
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imm_xor_or <= f0_xxx0xx ;
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imm_and_or <= f0_xxxx0x ;
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xtd_nor <= f1_xxx11 ;
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xtd_eqv_orc_nand <= f1_x1xx0 ;
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xtd_nand <= f1_x1x1x ;
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xtd_nand_or_orc <= f1_xx1xx ;
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xtd_andc_xor_or <= f1_xxx01 ;
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xtd_and_eqv_orc <= f1_xxx00 ;
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xtd_or_orc <= f1_xx10x ;
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xtd_xor_or <= f1_x1xx1 ;
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with cmp_byt select
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dec_alu_rf1_log_fcn <= "1001" when '1',
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rf1_log_fcn when others;
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rf1_log_fcn(0) <= (xtd_log and xtd_nor ) or -- xtd_log nor
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(xtd_log and xtd_eqv_orc_nand ) or -- xtd_log eqv,orc,nand
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(cmp_byt ) ; -- xnor
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rf1_log_fcn(1) <= (xtd_log and xtd_xor_or ) or -- xtd_log xor,or
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(xtd_log and xtd_nand ) or -- xtd_log nand
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(imm_log and imm_xor_or ) or -- xor,or
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(rotlw_pass ) or -- pass rlwimi
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(rotld_pass ) ; -- pass rldimi
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rf1_log_fcn(2) <= (xtd_log and xtd_andc_xor_or ) or -- xtd_log andc,xor,or
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(xtd_log and xtd_nand_or_orc ) or -- xtd_log nand_or_orc
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(imm_log and imm_xor_or ) ; -- xor,or
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rf1_log_fcn(3) <= (cmp_byt ) or -- xnor
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(xtd_log and xtd_and_eqv_orc ) or -- xtd_log and,eqv_orc
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(xtd_log and xtd_or_orc ) or -- xtd_log or,orc
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(imm_log and imm_and_or ) or -- and,or
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(rotlw_pass ) or -- pass rlwimi
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(rotld_pass ) ; -- pass rldimi
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dec_alu_rf1_chk_shov_dw <= (sh_rb_dw );
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dec_alu_rf1_chk_shov_wd <= (sh_rb_wd );
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-----------------------------------------------
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dec_alu_rf1_me_ins_b(0 to 5) <= not me_ins(0 to 5) ;
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me_ins(0) <= ( rotlw ) or -- force_msb
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( i(26) and sel_ins_me_hi ) or
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( not i(30) and sel_ins_amt_hi ) ;
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me_ins(1 to 5) <= ( i(26 to 30) and (1 to 5=> sel_ins_me_lo_wd) ) or
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( i(21 to 25) and (1 to 5=> sel_ins_me_lo_dw) ) or
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( not i(16 to 20) and (1 to 5=> sel_ins_amt_lo ) ) ;
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sel_ins_me_lo_wd <= rotlw ;
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sel_ins_me_lo_dw <= rld_cr or rld_icr ;
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sel_ins_amt_lo <= rld_ic or rld_imi or sh_lft_rb ;
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sel_ins_amt_hi <= rld_ic or rld_imi or sh_lft_rb_dw ;
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sel_ins_me_hi <= rld_cr or rld_icr ;
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dec_alu_rf1_use_me_rb_hi <= ( sh_lft_rb_dw );
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dec_alu_rf1_use_me_rb_lo <= ( sh_lft_rb );
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dec_alu_rf1_use_me_ins_hi <= rld_cr or rld_icr or rld_imi or rld_ic or rotlw or sh_lft_imm_dw ;
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dec_alu_rf1_use_me_ins_lo <= rld_cr or rld_icr or rld_imi or rld_ic or rotlw or sh_lft_imm ;
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rld_icl <= rotld and not i(27) and not i(28) and not i(29) ;
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rld_icr <= rotld and not i(27) and not i(28) and i(29) ;
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rld_ic <= rotld and not i(27) and i(28) and not i(29) ;
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rld_imi <= rotld and not i(27) and i(28) and i(29) ;
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rld_cl <= rotld and i(27) and not i(30);
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rld_cr <= rotld and i(27) and i(30);
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-----------------------------------------------
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dec_alu_rf1_mb_ins(0) <= ( i(26) and rot_imm_mb ) or
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( i(30) and shift_imm ) or
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( rotlw ) or -- force_msb
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( wd_if_sh ) ; -- force_msb
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dec_alu_rf1_mb_ins(1 to 5) <= ( i(21 to 25) and (1 to 5=> rot_imm_mb ) ) or
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( i(16 to 20) and (1 to 5=> shift_imm ) ) ;
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rot_imm_mb <= ( rotlw ) or
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( rld_cl or rld_icl or rld_ic or rld_imi ) ;
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dec_alu_rf1_use_mb_rb_lo <= sh_rgt_rb ;
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dec_alu_rf1_use_mb_rb_hi <= sh_rgt_rb_dw ;
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dec_alu_rf1_use_mb_ins_hi <= rld_cl or rld_icl or rld_imi or rld_ic or rotlw or sh_rgt_imm_dw or wd_if_sh;
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dec_alu_rf1_use_mb_ins_lo <= rld_cl or rld_icl or rld_imi or rld_ic or rotlw or sh_rgt_imm ;
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-----------------------------------------------
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dec_alu_rf1_use_rb_amt_hi <= ( rld_cr ) or
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( rld_cl ) or
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( sh_rb_dw ) ;
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dec_alu_rf1_use_rb_amt_lo <= ( rld_cr ) or
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( rld_cl ) or
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( rotlw_nm ) or -- rlwnm
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( sh_rb ) ;
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dec_alu_rf1_sh_amt(0) <= i(30) and not sh_word_int ;
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dec_alu_rf1_sh_amt(1 to 5) <= i(16 to 20) ;
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-----------------------------------------------
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rotld_en_mbgtme <= rld_imi or rld_ic ;
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dec_alu_rf1_mb_gt_me <= (mb_gt_me_cmp_wd and rotlw ) or
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(mb_gt_me_cmp_dw and rotld_en_mbgtme ) ; -- rldic,rldimi
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---------------------------------------------
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gt5_in1(1 to 5) <= i(21 to 25) ; -- mb
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gt5_in0(1 to 5) <= not i(26 to 30) ; -- me
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gt6_in1(0 to 5) <= i(26) & i(21 to 25) ; -- mb
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gt6_in0(0 to 5) <= i(30) & i(16 to 20) ; -- me not( not amt )
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--------------------------------------------
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gt5_g_b(1 to 5) <= not( gt5_in0(1 to 5) and gt5_in1(1 to 5) );
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gt5_t_b(1 to 4) <= not( gt5_in0(1 to 4) or gt5_in1(1 to 4) );
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gt5_g_45 <= not( gt5_g_b(4) and (gt5_t_b(4) or gt5_g_b(5) ) );
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|
gt5_g_23 <= not( gt5_g_b(2) and (gt5_t_b(2) or gt5_g_b(3) ) );
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|
gt5_g_1 <= not( gt5_g_b(1) );
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|
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gt5_t_23 <= not( gt5_t_b(2) or gt5_t_b(3) );
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|
gt5_t_1 <= not( gt5_t_b(1) );
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|
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|
mb_gt_me_cmp_wd0_b <= not( gt5_g_1 );
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|
mb_gt_me_cmp_wd1_b <= not( gt5_g_23 and gt5_t_1 );
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|
mb_gt_me_cmp_wd2_b <= not( gt5_g_45 and gt5_t_1 and gt5_t_23 );
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|
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mb_gt_me_cmp_wd <= not( mb_gt_me_cmp_wd0_b and mb_gt_me_cmp_wd1_b and mb_gt_me_cmp_wd2_b );
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|
|
|
----------------------------------------------
|
|
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gt6_g_b(0 to 5) <= not( gt6_in0(0 to 5) and gt6_in1(0 to 5) );
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|
gt6_t_b(0 to 4) <= not( gt6_in0(0 to 4) or gt6_in1(0 to 4) );
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|
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|
gt6_g_45 <= not( gt6_g_b(4) and (gt6_t_b(4) or gt6_g_b(5) ) );
|
|
gt6_g_23 <= not( gt6_g_b(2) and (gt6_t_b(2) or gt6_g_b(3) ) );
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|
gt6_g_01 <= not( gt6_g_b(0) and (gt6_t_b(0) or gt6_g_b(1) ) );
|
|
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gt6_t_23 <= not( gt6_t_b(2) or gt6_t_b(3) );
|
|
gt6_t_01 <= not( gt6_t_b(0) or gt6_t_b(1) );
|
|
|
|
mb_gt_me_cmp_dw0_b <= not( gt6_g_01 );
|
|
mb_gt_me_cmp_dw1_b <= not( gt6_g_23 and gt6_t_01 );
|
|
mb_gt_me_cmp_dw2_b <= not( gt6_g_45 and gt6_t_01 and gt6_t_23 );
|
|
|
|
mb_gt_me_cmp_dw <= not( mb_gt_me_cmp_dw0_b and mb_gt_me_cmp_dw1_b and mb_gt_me_cmp_dw2_b );
|
|
|
|
----------------------------------------------
|
|
|
|
mark_unused(i(6 to 15));
|
|
mark_unused(i(31));
|
|
|
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|
end architecture xuq_dec_dcdmrg;
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