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155 lines
7.8 KiB
VHDL
155 lines
7.8 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU ECC Generation Macro
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--
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library ieee,ibm,support;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_function_support.all;
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entity xuq_eccgen is
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generic(
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regsize : integer := 64);
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port(
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din : in std_ulogic_vector(0 to regsize+8-(64/regsize));
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Syn : out std_ulogic_vector(0 to 8-(64/regsize))
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_eccgen;
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architecture xuq_eccgen of xuq_eccgen is
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begin
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ecc64 : if regsize = 64 generate
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signal e : std_ulogic_vector(0 to 71); -- syndrome bits inverted
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signal l1term : std_ulogic_vector(0 to 22);
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begin
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-- ====================================================================
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-- 64 data bits, 8 check bits
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-- single bit error correction, double bit error detection
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-- ====================================================================
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-- ecc matrix description
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-- ====================================================================
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-- syn 0 111011010011101001100101101101001100101101001011001101001110100110000000
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-- syn 1 110110101011010101010101011010101010101010101010101010101101010101000000
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-- syn 2 101101100110110011001100110110011001100110011001100110011011001100100000
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-- syn 3 011100011110001111000011110001111000011110000111100001111000111100010000
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-- syn 4 000011111110000000111111110000000111111110000000011111111000000000001000
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-- syn 5 000000000001111111111111110000000000000001111111111111111000000000000100
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-- syn 6 000000000000000000000000001111111111111111111111111111111000000000000010
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-- syn 7 000000000000000000000000000000000000000000000000000000000111111100000001
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e(0 to 71) <= din(0 to 71);
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l1term(0) <= parity_map(e(0)&e(10)&e(17)&e(21)&e(32)&e(36)&e(44)&e(56));
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l1term(1) <= parity_map(e(22)&e(23)&e(24)&e(25)&e(53)&e(54)&e(55)&e(56));
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l1term(2) <= parity_map(e(1)&e(4)&e(11)&e(23)&e(26)&e(38)&e(46)&e(50));
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l1term(3) <= parity_map(e(2)&e(5)&e(12)&e(24)&e(27)&e(39)&e(47)&e(51));
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l1term(4) <= parity_map(e(3)&e(6)&e(13)&e(25)&e(28)&e(40)&e(48)&e(52));
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l1term(5) <= parity_map(e(7)&e(8)&e(9)&e(10)&e(37)&e(38)&e(39)&e(40));
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l1term(6) <= parity_map(e(14)&e(15)&e(16)&e(17)&e(45)&e(46)&e(47)&e(48));
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l1term(7) <= parity_map(e(18)&e(19)&e(20)&e(21)&e(49)&e(50)&e(51)&e(52));
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l1term(8) <= parity_map(e(7)&e(14)&e(18)&e(29)&e(33)&e(41)&e(53)&e(57));
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l1term(9) <= parity_map(e(58)&e(60)&e(63)&e(64));
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l1term(10) <= parity_map(e(8)&e(15)&e(19)&e(30)&e(34)&e(42)&e(54)&e(57));
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l1term(11) <= parity_map(e(59)&e(61)&e(63)&e(65));
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l1term(12) <= parity_map(e(9)&e(16)&e(20)&e(31)&e(35)&e(43)&e(55)&e(58));
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l1term(13) <= parity_map(e(59)&e(62)&e(63)&e(66));
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l1term(14) <= parity_map(e(1)&e(2)&e(3)&e(29)&e(30)&e(31)&e(32)&e(60));
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l1term(15) <= parity_map(e(61)&e(62)&e(63)&e(67));
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l1term(16) <= parity_map(e(4)&e(5)&e(6)&e(33)&e(34)&e(35)&e(36)&e(68));
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l1term(17) <= parity_map(e(11)&e(12)&e(13)&e(41)&e(42)&e(43)&e(44)&e(69));
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l1term(18) <= parity_map(e(26)&e(27)&e(28)&e(29)&e(30)&e(31)&e(32)&e(33));
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l1term(19) <= parity_map(e(34)&e(35)&e(36)&e(37)&e(38)&e(39)&e(40)&e(41));
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l1term(20) <= parity_map(e(42)&e(43)&e(44)&e(45)&e(46)&e(47)&e(48)&e(49));
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l1term(21) <= parity_map(e(50)&e(51)&e(52)&e(53)&e(54)&e(55)&e(56)&e(70));
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l1term(22) <= parity_map(e(57)&e(58)&e(59)&e(60)&e(61)&e(62)&e(63)&e(71));
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Syn(0) <= parity_map(l1term(0)&l1term(2)&l1term(3)&l1term(8)&l1term(9));
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Syn(1) <= parity_map(l1term(0)&l1term(2)&l1term(4)&l1term(10)&l1term(11));
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Syn(2) <= parity_map(l1term(0)&l1term(3)&l1term(4)&l1term(12)&l1term(13));
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Syn(3) <= parity_map(l1term(1)&l1term(5)&l1term(6)&l1term(14)&l1term(15));
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Syn(4) <= parity_map(l1term(1)&l1term(5)&l1term(7)&l1term(16));
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Syn(5) <= parity_map(l1term(1)&l1term(6)&l1term(7)&l1term(17));
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Syn(6) <= parity_map(l1term(18)&l1term(19)&l1term(20)&l1term(21));
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Syn(7) <= l1term(22);
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end generate;
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ecc32 : if regsize = 32 generate
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signal e : std_ulogic_vector(0 to 38); -- syndrome bits inverted
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signal l1term : std_ulogic_vector(0 to 13);
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begin
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-- ====================================================================
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-- 32 Data Bits, 7 Check bits
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-- Single bit error correction, Double bit error detection
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-- ====================================================================
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-- ECC Matrix Description
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-- ====================================================================
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-- Syn 0 111011010011101001100101101101001000000
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-- Syn 1 110110101011010101010101011010100100000
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-- Syn 2 101101100110110011001100110110010010000
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-- Syn 3 011100011110001111000011110001110001000
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-- Syn 4 000011111110000000111111110000000000100
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-- Syn 5 000000000001111111111111110000000000010
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-- Syn 6 000000000000000000000000001111110000001
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e(0 to 38) <= din(0 to 38);
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l1term(0) <= parity_map(e(0)&e(1)&e(4)&e(10)&e(11)&e(17)&e(21)&e(23));
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l1term(1) <= parity_map(e(2)&e(3)&e(9)&e(10)&e(16)&e(17)&e(24)&e(25));
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l1term(2) <= parity_map(e(18)&e(19)&e(20)&e(21)&e(22)&e(23)&e(24)&e(25));
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l1term(3) <= parity_map(e(2)&e(5)&e(7)&e(12)&e(14)&e(18)&e(24)&e(26));
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l1term(4) <= parity_map(e(27)&e(29)&e(32));
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l1term(5) <= parity_map(e(3)&e(6)&e(8)&e(13)&e(15)&e(19)&e(25)&e(26));
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l1term(6) <= parity_map(e(28)&e(30)&e(33));
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l1term(7) <= parity_map(e(0)&e(5)&e(6)&e(12)&e(13)&e(20)&e(21)&e(27));
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l1term(8) <= parity_map(e(28)&e(31)&e(34));
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l1term(9) <= parity_map(e(1)&e(7)&e(8)&e(14)&e(15)&e(22)&e(23)&e(29));
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l1term(10) <= parity_map(e(30)&e(31)&e(35));
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l1term(11) <= parity_map(e(4)&e(5)&e(6)&e(7)&e(8)&e(9)&e(10)&e(36));
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l1term(12) <= parity_map(e(11)&e(12)&e(13)&e(14)&e(15)&e(16)&e(17)&e(37));
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l1term(13) <= parity_map(e(26)&e(27)&e(28)&e(29)&e(30)&e(31)&e(38));
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Syn(0) <= parity_map(l1term(0)&l1term(3)&l1term(4));
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Syn(1) <= parity_map(l1term(0)&l1term(5)&l1term(6));
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Syn(2) <= parity_map(l1term(1)&l1term(7)&l1term(8));
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Syn(3) <= parity_map(l1term(1)&l1term(9)&l1term(10));
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Syn(4) <= parity_map(l1term(2)&l1term(11));
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Syn(5) <= parity_map(l1term(2)&l1term(12));
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Syn(6) <= l1term(13);
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end generate;
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end xuq_eccgen;
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