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296 lines
14 KiB
VHDL
296 lines
14 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU SPR - Wrapper
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--
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library ieee,ibm,support,work,tri;
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use ieee.std_logic_1164.all;
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use support.power_logic_pkg.all;
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use ibm.std_ulogic_function_support.all;
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use tri.tri_latches_pkg.all;
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entity xuq_fxu_spr is
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generic(
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hvmode : integer := 1;
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a2mode : integer := 1;
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expand_type : integer := 2;
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threads : integer := 4;
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regsize : integer := 64;
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eff_ifar : integer := 62);
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port(
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nclk : in clk_logic;
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d_mode_dc : in std_ulogic;
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delay_lclkr_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic;
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mpw2_dc_b : in std_ulogic;
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func_sl_force : in std_ulogic;
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func_sl_thold_0_b : in std_ulogic;
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func_nsl_force : in std_ulogic;
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func_nsl_thold_0_b : in std_ulogic;
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sg_0 : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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-- Decode
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ex1_tid : in std_ulogic_vector(0 to threads-1);
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ex1_instr : in std_ulogic_vector(11 to 20);
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dec_spr_ex1_is_mfspr : in std_ulogic;
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dec_spr_ex1_is_mtspr : in std_ulogic;
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-- Write Interface
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ex6_val : in std_ulogic_vector(0 to threads-1);
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ex6_spr_wd : in std_ulogic_vector(64-regsize to 63);
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-- Read Data
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fspr_byp_ex3_spr_rt : out std_ulogic_vector(64-regsize to 63);
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mux_spr_ex2_rt : in std_ulogic_vector(64-regsize to 63);
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ex2_is_any_load_dac : in std_ulogic;
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ex2_is_any_store_dac : in std_ulogic;
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-- DAC
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xu_lsu_ex4_dvc1_en : out std_ulogic;
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xu_lsu_ex4_dvc2_en : out std_ulogic;
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-- For Stores only, not gated by dvc*_en
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lsu_xu_ex2_dvc1_st_cmp : in std_ulogic_vector(8-regsize/8 to 7);
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lsu_xu_ex2_dvc2_st_cmp : in std_ulogic_vector(8-regsize/8 to 7);
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-- For load hits only, gated by dvc*_en
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lsu_xu_ex8_dvc1_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7);
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lsu_xu_ex8_dvc2_ld_cmp : in std_ulogic_vector(8-regsize/8 to 7);
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-- For reloads only, all signals are gated by dvc*_en
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lsu_xu_rel_dvc1_en : in std_ulogic;
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lsu_xu_rel_dvc2_en : in std_ulogic;
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lsu_xu_rel_dvc_thrd_id : in std_ulogic_vector(0 to 3);
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lsu_xu_rel_dvc1_cmp : in std_ulogic_vector(8-regsize/8 to 7);
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lsu_xu_rel_dvc2_cmp : in std_ulogic_vector(8-regsize/8 to 7);
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fxu_cpl_ex3_dac1r_cmpr_async : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac2r_cmpr_async : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac1r_cmpr : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac2r_cmpr : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac3r_cmpr : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac4r_cmpr : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac1w_cmpr : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac2w_cmpr : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac3w_cmpr : out std_ulogic_vector(0 to threads-1);
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fxu_cpl_ex3_dac4w_cmpr : out std_ulogic_vector(0 to threads-1);
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-- SPRs
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spr_bit_act : in std_ulogic;
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spr_msr_pr : in std_ulogic_vector(0 to threads-1);
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spr_msr_ds : in std_ulogic_vector(0 to threads-1);
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spr_dbcr0_dac1 : in std_ulogic_vector(0 to 2*threads-1);
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spr_dbcr0_dac2 : in std_ulogic_vector(0 to 2*threads-1);
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spr_dbcr0_dac3 : in std_ulogic_vector(0 to 2*threads-1);
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spr_dbcr0_dac4 : in std_ulogic_vector(0 to 2*threads-1);
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spr_dbcr3_ivc : out std_ulogic_vector(0 to threads-1);
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-- Power
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vdd : inout power_logic;
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gnd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_fxu_spr;
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architecture xuq_fxu_spr of xuq_fxu_spr is
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signal siv : std_ulogic_vector(0 to threads);
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signal sov : std_ulogic_vector(0 to threads);
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-- Signals
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signal cspr_tspr_ex6_is_mtspr : std_ulogic;
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signal cspr_tspr_ex6_instr : std_ulogic_vector(11 to 20);
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signal cspr_tspr_ex2_instr : std_ulogic_vector(11 to 20);
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signal tspr_cspr_ex2_tspr_rt : std_ulogic_vector(0 to regsize*threads-1);
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signal tspr_cspr_dbcr2_dac1us : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr2_dac1er : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr2_dac2us : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr2_dac2er : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr3_dac3us : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr3_dac3er : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr3_dac4us : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr3_dac4er : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr2_dac12m : std_ulogic_vector(0 to threads-1);
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signal tspr_cspr_dbcr3_dac34m : std_ulogic_vector(0 to threads-1);
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signal tspr_cspr_dbcr2_dvc1m : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr2_dvc2m : std_ulogic_vector(0 to 2*threads-1);
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signal tspr_cspr_dbcr2_dvc1be : std_ulogic_vector(0 to 8*threads-1);
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signal tspr_cspr_dbcr2_dvc2be : std_ulogic_vector(0 to 8*threads-1);
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begin
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xu_fxu_spr_cspr : entity work.xuq_fxu_spr_cspr(xuq_fxu_spr_cspr)
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generic map(
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hvmode => hvmode,
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a2mode => a2mode,
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expand_type => expand_type,
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threads => threads,
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regsize => regsize,
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eff_ifar => eff_ifar)
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port map(
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nclk => nclk,
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d_mode_dc => d_mode_dc,
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delay_lclkr_dc => delay_lclkr_dc,
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mpw1_dc_b => mpw1_dc_b,
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mpw2_dc_b => mpw2_dc_b,
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func_sl_force => func_sl_force,
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func_sl_thold_0_b => func_sl_thold_0_b,
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func_nsl_force => func_nsl_force,
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func_nsl_thold_0_b => func_nsl_thold_0_b,
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sg_0 => sg_0,
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scan_in => siv(threads),
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scan_out => sov(threads),
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-- Decode
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ex1_instr => ex1_instr,
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ex1_tid => ex1_tid,
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dec_spr_ex1_is_mfspr => dec_spr_ex1_is_mfspr,
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dec_spr_ex1_is_mtspr => dec_spr_ex1_is_mtspr,
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-- Write Interface
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ex6_valid => ex6_val,
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ex6_spr_wd => ex6_spr_wd,
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-- SPRT Interface
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cspr_tspr_ex6_is_mtspr => cspr_tspr_ex6_is_mtspr,
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cspr_tspr_ex6_instr => cspr_tspr_ex6_instr,
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cspr_tspr_ex2_instr => cspr_tspr_ex2_instr,
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-- Read Data
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tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt,
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fspr_byp_ex3_spr_rt => fspr_byp_ex3_spr_rt,
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mux_spr_ex2_rt => mux_spr_ex2_rt,
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ex2_is_any_load_dac => ex2_is_any_load_dac,
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ex2_is_any_store_dac => ex2_is_any_store_dac,
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-- DAC
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xu_lsu_ex4_dvc1_en => xu_lsu_ex4_dvc1_en,
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xu_lsu_ex4_dvc2_en => xu_lsu_ex4_dvc2_en,
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lsu_xu_ex2_dvc1_st_cmp => lsu_xu_ex2_dvc1_st_cmp,
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lsu_xu_ex2_dvc2_st_cmp => lsu_xu_ex2_dvc2_st_cmp,
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lsu_xu_ex8_dvc1_ld_cmp => lsu_xu_ex8_dvc1_ld_cmp,
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lsu_xu_ex8_dvc2_ld_cmp => lsu_xu_ex8_dvc2_ld_cmp,
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lsu_xu_rel_dvc1_en => lsu_xu_rel_dvc1_en,
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lsu_xu_rel_dvc2_en => lsu_xu_rel_dvc2_en,
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lsu_xu_rel_dvc_thrd_id => lsu_xu_rel_dvc_thrd_id,
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lsu_xu_rel_dvc1_cmp => lsu_xu_rel_dvc1_cmp,
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lsu_xu_rel_dvc2_cmp => lsu_xu_rel_dvc2_cmp,
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fxu_cpl_ex3_dac1r_cmpr_async => fxu_cpl_ex3_dac1r_cmpr_async,
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fxu_cpl_ex3_dac2r_cmpr_async => fxu_cpl_ex3_dac2r_cmpr_async,
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fxu_cpl_ex3_dac1r_cmpr => fxu_cpl_ex3_dac1r_cmpr,
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fxu_cpl_ex3_dac2r_cmpr => fxu_cpl_ex3_dac2r_cmpr,
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fxu_cpl_ex3_dac3r_cmpr => fxu_cpl_ex3_dac3r_cmpr,
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fxu_cpl_ex3_dac4r_cmpr => fxu_cpl_ex3_dac4r_cmpr,
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fxu_cpl_ex3_dac1w_cmpr => fxu_cpl_ex3_dac1w_cmpr,
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fxu_cpl_ex3_dac2w_cmpr => fxu_cpl_ex3_dac2w_cmpr,
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fxu_cpl_ex3_dac3w_cmpr => fxu_cpl_ex3_dac3w_cmpr,
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fxu_cpl_ex3_dac4w_cmpr => fxu_cpl_ex3_dac4w_cmpr,
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-- SPRs
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spr_bit_act => spr_bit_act,
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spr_msr_pr => spr_msr_pr,
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spr_msr_ds => spr_msr_ds,
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spr_dbcr0_dac1 => spr_dbcr0_dac1,
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spr_dbcr0_dac2 => spr_dbcr0_dac2,
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spr_dbcr0_dac3 => spr_dbcr0_dac3,
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spr_dbcr0_dac4 => spr_dbcr0_dac4,
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tspr_cspr_dbcr2_dac1us => tspr_cspr_dbcr2_dac1us,
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tspr_cspr_dbcr2_dac1er => tspr_cspr_dbcr2_dac1er,
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tspr_cspr_dbcr2_dac2us => tspr_cspr_dbcr2_dac2us,
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tspr_cspr_dbcr2_dac2er => tspr_cspr_dbcr2_dac2er,
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tspr_cspr_dbcr3_dac3us => tspr_cspr_dbcr3_dac3us,
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tspr_cspr_dbcr3_dac3er => tspr_cspr_dbcr3_dac3er,
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tspr_cspr_dbcr3_dac4us => tspr_cspr_dbcr3_dac4us,
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tspr_cspr_dbcr3_dac4er => tspr_cspr_dbcr3_dac4er,
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tspr_cspr_dbcr2_dac12m => tspr_cspr_dbcr2_dac12m,
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tspr_cspr_dbcr3_dac34m => tspr_cspr_dbcr3_dac34m,
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tspr_cspr_dbcr2_dvc1m => tspr_cspr_dbcr2_dvc1m,
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tspr_cspr_dbcr2_dvc2m => tspr_cspr_dbcr2_dvc2m,
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tspr_cspr_dbcr2_dvc1be => tspr_cspr_dbcr2_dvc1be,
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tspr_cspr_dbcr2_dvc2be => tspr_cspr_dbcr2_dvc2be,
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-- Power
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vdd => vdd,
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gnd => gnd
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);
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thread : for t in 0 to threads-1 generate
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xu_fxu_spr_tspr : entity work.xuq_fxu_spr_tspr(xuq_fxu_spr_tspr)
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generic map(
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hvmode => hvmode,
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a2mode => a2mode,
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expand_type => expand_type,
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regsize => regsize,
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eff_ifar => eff_ifar)
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port map(
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nclk => nclk,
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d_mode_dc => d_mode_dc,
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delay_lclkr_dc => delay_lclkr_dc,
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mpw1_dc_b => mpw1_dc_b,
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mpw2_dc_b => mpw2_dc_b,
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func_sl_force => func_sl_force,
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func_sl_thold_0_b => func_sl_thold_0_b,
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sg_0 => sg_0,
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scan_in => siv(t),
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scan_out => sov(t),
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-- Read Interface
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cspr_tspr_ex2_instr => cspr_tspr_ex2_instr,
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tspr_cspr_ex2_tspr_rt => tspr_cspr_ex2_tspr_rt(regsize*t to regsize*(t+1)-1),
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-- Write Interface
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ex6_val => ex6_val(t),
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cspr_tspr_ex6_is_mtspr => cspr_tspr_ex6_is_mtspr,
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cspr_tspr_ex6_instr => cspr_tspr_ex6_instr,
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ex6_spr_wd => ex6_spr_wd,
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-- SPRs
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tspr_cspr_dbcr2_dac1us => tspr_cspr_dbcr2_dac1us(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr2_dac1er => tspr_cspr_dbcr2_dac1er(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr2_dac2us => tspr_cspr_dbcr2_dac2us(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr2_dac2er => tspr_cspr_dbcr2_dac2er(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr3_dac3us => tspr_cspr_dbcr3_dac3us(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr3_dac3er => tspr_cspr_dbcr3_dac3er(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr3_dac4us => tspr_cspr_dbcr3_dac4us(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr3_dac4er => tspr_cspr_dbcr3_dac4er(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr2_dac12m => tspr_cspr_dbcr2_dac12m(t),
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tspr_cspr_dbcr3_dac34m => tspr_cspr_dbcr3_dac34m(t),
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tspr_cspr_dbcr2_dvc1m => tspr_cspr_dbcr2_dvc1m(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr2_dvc2m => tspr_cspr_dbcr2_dvc2m(2*t to 2*(t+1)-1),
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tspr_cspr_dbcr2_dvc1be => tspr_cspr_dbcr2_dvc1be(8*t to 8*(t+1)-1),
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tspr_cspr_dbcr2_dvc2be => tspr_cspr_dbcr2_dvc2be(8*t to 8*(t+1)-1),
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spr_dbcr3_ivc => spr_dbcr3_ivc(t),
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-- Power
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vdd => vdd,
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gnd => gnd
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);
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end generate;
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siv(0 to threads) <= sov(1 to threads) & scan_in;
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scan_out <= sov(0);
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end architecture xuq_fxu_spr;
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