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315 lines
13 KiB
VHDL
315 lines
13 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU SPR - per thread register slice
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--
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library ieee,ibm,support,work,tri;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use support.power_logic_pkg.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use tri.tri_latches_pkg.all;
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use work.xuq_pkg.all;
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entity xuq_fxu_spr_tspr is
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generic(
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hvmode : integer := 1;
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a2mode : integer := 1;
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expand_type : integer := 2;
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regsize : integer := 64;
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eff_ifar : integer := 62);
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port(
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nclk : in clk_logic;
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d_mode_dc : in std_ulogic;
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delay_lclkr_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic;
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mpw2_dc_b : in std_ulogic;
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func_sl_force : in std_ulogic;
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func_sl_thold_0_b : in std_ulogic;
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sg_0 : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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-- Read Interface
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cspr_tspr_ex2_instr : in std_ulogic_vector(11 to 20);
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tspr_cspr_ex2_tspr_rt : out std_ulogic_vector(64-regsize to 63);
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-- Write Interface
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ex6_val : in std_ulogic;
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cspr_tspr_ex6_is_mtspr : in std_ulogic;
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cspr_tspr_ex6_instr : in std_ulogic_vector(11 to 20);
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ex6_spr_wd : in std_ulogic_vector(64-regsize to 63);
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-- SPRs
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tspr_cspr_dbcr2_dac1us : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr2_dac1er : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr2_dac2us : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr2_dac2er : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr3_dac3us : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr3_dac3er : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr3_dac4us : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr3_dac4er : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr2_dac12m : out std_ulogic;
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tspr_cspr_dbcr3_dac34m : out std_ulogic;
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tspr_cspr_dbcr2_dvc1m : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr2_dvc2m : out std_ulogic_vector(0 to 1);
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tspr_cspr_dbcr2_dvc1be : out std_ulogic_vector(0 to 7);
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tspr_cspr_dbcr2_dvc2be : out std_ulogic_vector(0 to 7);
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spr_dbcr3_ivc : out std_ulogic;
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-- Power
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vdd : inout power_logic;
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gnd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_fxu_spr_tspr;
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architecture xuq_fxu_spr_tspr of xuq_fxu_spr_tspr is
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-- Types
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subtype DO is std_ulogic_vector(65-regsize to 64);
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-- SPR Registers
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signal dbcr2_d , dbcr2_q : std_ulogic_vector(35 to 63);
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signal dbcr3_d , dbcr3_q : std_ulogic_vector(54 to 63);
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-- FUNC Scanchain
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constant dbcr2_offset : natural := 0;
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constant dbcr3_offset : natural := dbcr2_offset + dbcr2_q'length*a2mode;
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constant last_reg_offset : natural := dbcr3_offset + dbcr3_q'length;
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constant scan_right : integer := last_reg_offset;
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signal siv : std_ulogic_vector(0 to scan_right-1);
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signal sov : std_ulogic_vector(0 to scan_right-1);
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-- Signals
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signal tiup : std_ulogic;
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signal tidn : std_ulogic_vector(00 to 63);
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signal ex2_instr : std_ulogic_vector(11 to 20);
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signal ex6_is_mtspr : std_ulogic;
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signal ex6_instr : std_ulogic_vector(11 to 20);
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-- Data
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signal spr_dbcr2_dac1us : std_ulogic_vector(0 to 1);
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signal spr_dbcr2_dac1er : std_ulogic_vector(0 to 1);
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signal spr_dbcr2_dac2us : std_ulogic_vector(0 to 1);
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signal spr_dbcr2_dac2er : std_ulogic_vector(0 to 1);
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signal spr_dbcr2_dac12m : std_ulogic;
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signal spr_dbcr2_dvc1m : std_ulogic_vector(0 to 1);
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signal spr_dbcr2_dvc2m : std_ulogic_vector(0 to 1);
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signal spr_dbcr2_dvc1be : std_ulogic_vector(0 to 7);
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signal spr_dbcr2_dvc2be : std_ulogic_vector(0 to 7);
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signal spr_dbcr3_dac3us : std_ulogic_vector(0 to 1);
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signal spr_dbcr3_dac3er : std_ulogic_vector(0 to 1);
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signal spr_dbcr3_dac4us : std_ulogic_vector(0 to 1);
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signal spr_dbcr3_dac4er : std_ulogic_vector(0 to 1);
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signal spr_dbcr3_dac34m : std_ulogic;
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signal ex6_dbcr2_di : std_ulogic_vector(dbcr2_q'range);
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signal ex6_dbcr3_di : std_ulogic_vector(dbcr3_q'range);
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signal
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ex2_dbcr2_rdec , ex2_dbcr3_rdec
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: std_ulogic;
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signal
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ex2_dbcr2_re , ex2_dbcr3_re
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: std_ulogic;
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signal
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ex6_dbcr2_wdec , ex6_dbcr3_wdec
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: std_ulogic;
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signal
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ex6_dbcr2_we , ex6_dbcr3_we
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: std_ulogic;
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signal
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dbcr2_act , dbcr3_act
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: std_ulogic;
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signal
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dbcr2_do , dbcr3_do
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: std_ulogic_vector(0 to 64);
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begin
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tiup <= '1';
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tidn <= (others=>'0');
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ex2_instr <= cspr_tspr_ex2_instr;
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ex6_is_mtspr <= cspr_tspr_ex6_is_mtspr;
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ex6_instr <= cspr_tspr_ex6_instr;
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-- SPR Input Control
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-- DBCR2
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dbcr2_act <= ex6_dbcr2_we;
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dbcr2_d <= ex6_dbcr2_di;
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-- DBCR3
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dbcr3_act <= ex6_dbcr3_we;
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dbcr3_d <= ex6_dbcr3_di;
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readmux_00 : if a2mode = 0 and hvmode = 0 generate
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tspr_cspr_ex2_tspr_rt <=
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(dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re ));
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end generate;
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readmux_01 : if a2mode = 0 and hvmode = 1 generate
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tspr_cspr_ex2_tspr_rt <=
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(dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re ));
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end generate;
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readmux_10 : if a2mode = 1 and hvmode = 0 generate
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tspr_cspr_ex2_tspr_rt <=
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(dbcr2_do(DO'range) and (DO'range => ex2_dbcr2_re )) or
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(dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re ));
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end generate;
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readmux_11 : if a2mode = 1 and hvmode = 1 generate
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tspr_cspr_ex2_tspr_rt <=
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(dbcr2_do(DO'range) and (DO'range => ex2_dbcr2_re )) or
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(dbcr3_do(DO'range) and (DO'range => ex2_dbcr3_re ));
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end generate;
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ex2_dbcr2_rdec <= (ex2_instr(11 to 20) = "1011001001"); -- 310
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ex2_dbcr3_rdec <= (ex2_instr(11 to 20) = "1000011010"); -- 848
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ex2_dbcr2_re <= ex2_dbcr2_rdec;
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ex2_dbcr3_re <= ex2_dbcr3_rdec;
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ex6_dbcr2_wdec <= (ex6_instr(11 to 20) = "1011001001"); -- 310
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ex6_dbcr3_wdec <= (ex6_instr(11 to 20) = "1000011010"); -- 848
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ex6_dbcr2_we <= ex6_val and ex6_is_mtspr and ex6_dbcr2_wdec;
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ex6_dbcr3_we <= ex6_val and ex6_is_mtspr and ex6_dbcr3_wdec;
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spr_dbcr2_dac1us <= dbcr2_q(35 to 36);
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spr_dbcr2_dac1er <= dbcr2_q(37 to 38);
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spr_dbcr2_dac2us <= dbcr2_q(39 to 40);
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spr_dbcr2_dac2er <= dbcr2_q(41 to 42);
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spr_dbcr2_dac12m <= dbcr2_q(43);
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spr_dbcr2_dvc1m <= dbcr2_q(44 to 45);
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spr_dbcr2_dvc2m <= dbcr2_q(46 to 47);
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spr_dbcr2_dvc1be <= dbcr2_q(48 to 55);
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spr_dbcr2_dvc2be <= dbcr2_q(56 to 63);
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spr_dbcr3_dac3us <= dbcr3_q(54 to 55);
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spr_dbcr3_dac3er <= dbcr3_q(56 to 57);
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spr_dbcr3_dac4us <= dbcr3_q(58 to 59);
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spr_dbcr3_dac4er <= dbcr3_q(60 to 61);
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spr_dbcr3_dac34m <= dbcr3_q(62);
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spr_dbcr3_ivc <= dbcr3_q(63);
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tspr_cspr_dbcr2_dac1us <= spr_dbcr2_dac1us;
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tspr_cspr_dbcr2_dac1er <= spr_dbcr2_dac1er;
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tspr_cspr_dbcr2_dac2us <= spr_dbcr2_dac2us;
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tspr_cspr_dbcr2_dac2er <= spr_dbcr2_dac2er;
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tspr_cspr_dbcr3_dac3us <= spr_dbcr3_dac3us;
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tspr_cspr_dbcr3_dac3er <= spr_dbcr3_dac3er;
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tspr_cspr_dbcr3_dac4us <= spr_dbcr3_dac4us;
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tspr_cspr_dbcr3_dac4er <= spr_dbcr3_dac4er;
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tspr_cspr_dbcr2_dac12m <= spr_dbcr2_dac12m;
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tspr_cspr_dbcr3_dac34m <= spr_dbcr3_dac34m;
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tspr_cspr_dbcr2_dvc1m <= spr_dbcr2_dvc1m;
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tspr_cspr_dbcr2_dvc2m <= spr_dbcr2_dvc2m;
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tspr_cspr_dbcr2_dvc1be <= spr_dbcr2_dvc1be;
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tspr_cspr_dbcr2_dvc2be <= spr_dbcr2_dvc2be;
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mark_unused(tiup);
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mark_unused(tidn);
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mark_unused(ex6_spr_wd);
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-- DBCR2
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ex6_dbcr2_di <= ex6_spr_wd(32 to 33) & --DAC1US
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ex6_spr_wd(34 to 35) & --DAC1ER
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ex6_spr_wd(36 to 37) & --DAC2US
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ex6_spr_wd(38 to 39) & --DAC2ER
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ex6_spr_wd(41 to 41) & --DAC12M
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ex6_spr_wd(44 to 45) & --DVC1M
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ex6_spr_wd(46 to 47) & --DVC2M
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ex6_spr_wd(48 to 55) & --DVC1BE
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ex6_spr_wd(56 to 63) ; --DVC2BE
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dbcr2_do <= tidn(0 to 0) &
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tidn(0 to 31) & --///
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dbcr2_q(35 to 36) & --DAC1US
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dbcr2_q(37 to 38) & --DAC1ER
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dbcr2_q(39 to 40) & --DAC2US
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dbcr2_q(41 to 42) & --DAC2ER
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tidn(40 to 40) & --///
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dbcr2_q(43 to 43) & --DAC12M
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tidn(42 to 43) & --///
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dbcr2_q(44 to 45) & --DVC1M
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dbcr2_q(46 to 47) & --DVC2M
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dbcr2_q(48 to 55) & --DVC1BE
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dbcr2_q(56 to 63) ; --DVC2BE
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-- DBCR3
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ex6_dbcr3_di <= ex6_spr_wd(32 to 33) & --DAC3US
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ex6_spr_wd(34 to 35) & --DAC3ER
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ex6_spr_wd(36 to 37) & --DAC4US
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ex6_spr_wd(38 to 39) & --DAC4ER
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ex6_spr_wd(41 to 41) & --DAC34M
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ex6_spr_wd(63 to 63) ; --IVC
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dbcr3_do <= tidn(0 to 0) &
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tidn(0 to 31) & --///
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dbcr3_q(54 to 55) & --DAC3US
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dbcr3_q(56 to 57) & --DAC3ER
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dbcr3_q(58 to 59) & --DAC4US
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dbcr3_q(60 to 61) & --DAC4ER
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tidn(40 to 40) & --///
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dbcr3_q(62 to 62) & --DAC34M
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tidn(42 to 62) & --///
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dbcr3_q(63 to 63) ; --IVC
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-- Unused Signals
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mark_unused(dbcr2_do(0 to 64-regsize));
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mark_unused(dbcr3_do(0 to 64-regsize));
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dbcr2_latch_gen : if a2mode = 1 generate
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dbcr2_latch : tri_ser_rlmreg_p
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generic map(width => dbcr2_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map(nclk => nclk, vd => vdd, gd => gnd,
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act => dbcr2_act,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(dbcr2_offset to dbcr2_offset + dbcr2_q'length-1),
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scout => sov(dbcr2_offset to dbcr2_offset + dbcr2_q'length-1),
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din => dbcr2_d,
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dout => dbcr2_q);
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end generate;
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dbcr2_latch_tie : if a2mode = 0 generate
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dbcr2_q <= (others=>'0');
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end generate;
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dbcr3_latch : tri_ser_rlmreg_p
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generic map(width => dbcr3_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map(nclk => nclk, vd => vdd, gd => gnd,
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act => dbcr3_act,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(dbcr3_offset to dbcr3_offset + dbcr3_q'length-1),
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scout => sov(dbcr3_offset to dbcr3_offset + dbcr3_q'length-1),
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din => dbcr3_d,
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dout => dbcr3_q);
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siv(0 to scan_right-1) <= sov(1 to scan_right-1) & scan_in;
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scan_out <= sov(0);
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end architecture xuq_fxu_spr_tspr;
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