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104 lines
4.2 KiB
VHDL
104 lines
4.2 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU LSU Compare Logic
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-- ###################################################################
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-- ## Address decoder
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-- ###################################################################
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LIBRARY ieee; USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY ibm;
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USE ibm.std_ulogic_support.all;
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USE ibm.std_ulogic_unsigned.all;
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USE ibm.std_ulogic_function_support.all;
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LIBRARY support;
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USE support.power_logic_pkg.all;
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LIBRARY tri; USE tri.tri_latches_pkg.all;
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entity xuq_lsu_cmp_cmp31 is
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generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other );
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port(
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d0 :in std_ulogic_vector(0 to 30);
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d1 :in std_ulogic_vector(0 to 30);
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eq :out std_ulogic
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);
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end xuq_lsu_cmp_cmp31; -- ENTITY
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architecture xuq_lsu_cmp_cmp31 of xuq_lsu_cmp_cmp31 is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal eq01 :std_ulogic_vector(0 to 30) ;
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signal eq03_b : std_ulogic_vector(0 to 11);
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signal eq06 : std_ulogic_vector(0 to 5);
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signal eq18_b : std_ulogic_vector(0 to 1);
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begin
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u_eq01: eq01(0 to 30) <= not( d0(0 to 30) xor d1(0 to 30) );
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u_eq03_00: eq03_b( 0) <= not( eq01( 0) and eq01( 1) and eq01( 2) );
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u_eq03_01: eq03_b( 1) <= not( eq01( 3) and eq01( 4) and eq01( 5) );
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u_eq03_02: eq03_b( 2) <= not( eq01( 6) and eq01( 7) and eq01( 8) );
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u_eq03_03: eq03_b( 3) <= not( eq01( 9) and eq01(10) and eq01(11) );
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u_eq03_04: eq03_b( 4) <= not( eq01(12) and eq01(13) and eq01(14) );
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u_eq03_05: eq03_b( 5) <= not( eq01(15) and eq01(16) and eq01(17) );
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u_eq03_06: eq03_b( 6) <= not( eq01(18) and eq01(19) and eq01(20) );
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u_eq03_07: eq03_b( 7) <= not( eq01(21) and eq01(22) );
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u_eq03_08: eq03_b( 8) <= not( eq01(23) and eq01(24) );
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u_eq03_09: eq03_b( 9) <= not( eq01(25) and eq01(26) );
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u_eq03_10: eq03_b(10) <= not( eq01(27) and eq01(28) );
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u_eq03_11: eq03_b(11) <= not( eq01(29) and eq01(30) );
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u_eq06_00: eq06( 0) <= not( eq03_b( 0) or eq03_b( 1) );
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u_eq06_01: eq06( 1) <= not( eq03_b( 2) or eq03_b( 3) );
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u_eq06_02: eq06( 2) <= not( eq03_b( 4) or eq03_b( 5) );
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u_eq06_03: eq06( 3) <= not( eq03_b( 6) or eq03_b( 7) );
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u_eq06_04: eq06( 4) <= not( eq03_b( 8) or eq03_b( 9) );
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u_eq06_05: eq06( 5) <= not( eq03_b(10) or eq03_b(11) );
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u_eq18_00: eq18_b( 0) <= not( eq06(0) and eq06(1) and eq06(2) );
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u_eq18_01: eq18_b( 1) <= not( eq06(3) and eq06(4) and eq06(5) );
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u_eq36_00: eq <= not( eq18_b( 0) or eq18_b( 1) ); -- output
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end; -- xuq_lsu_cmp_cmp31 ARCHITECTURE
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