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343 lines
14 KiB
VHDL
343 lines
14 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU LSU L1 Data Cache Array
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--
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library ibm, ieee, work, tri, support;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use tri.tri_latches_pkg.all;
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use support.power_logic_pkg.all;
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-- ##########################################################################################
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-- VHDL Contents
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-- 1) L1 D-Cache Array
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-- 2) Load Data Way Select Mux
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-- 3) Reload/Store Data select
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-- ##########################################################################################
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entity xuq_lsu_dc_arr is
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generic(expand_type : integer := 2; -- 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
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dc_size : natural := 14); -- 2^14 = 16384 Bytes L1 D$
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port(
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-- Acts to latches
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ex3_stg_act :in std_ulogic;
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ex4_stg_act :in std_ulogic;
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rel3_stg_act :in std_ulogic;
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rel4_stg_act :in std_ulogic;
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-- XUOP Signals
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ex3_p_addr :in std_ulogic_vector(64-(dc_size-3) to 58); -- EX3 L1 D$ Array Address
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ex3_byte_en :in std_ulogic_vector(0 to 31); -- EX3 Store Byte Enables
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ex4_256st_data :in std_ulogic_vector(0 to 255); -- EX4 Store Data that will be stored in L1 D$ Array
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ex4_parity_gen :in std_ulogic_vector(0 to 31); -- EX4 Parity Bits for XU/AXU store data
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ex4_load_hit :in std_ulogic; -- EX4 Instruction is a load hit
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ex5_stg_flush :in std_ulogic; -- EX5 Stage Flush
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-- Parity Error Inject
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inj_dcache_parity :in std_ulogic; -- Parity Error Inject
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-- Reload Signals
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ldq_rel_data_val :in std_ulogic;
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ldq_rel_addr :in std_ulogic_vector(64-(dc_size-3) to 58); -- Reload Array Address
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-- D$ Array Inputs
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dcarr_rd_data :in std_ulogic_vector(0 to 287); -- D$ Array Read Data
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-- D$ Array Outputs
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dcarr_bw :out std_ulogic_vector(0 to 287); -- D$ Array Bit Enables
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dcarr_addr :out std_ulogic_vector(64-(dc_size-3) to 58); -- D$ Array Address
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dcarr_wr_data :out std_ulogic_vector(0 to 287); -- D$ Array Write Data
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dcarr_bw_dly :out std_ulogic_vector(0 to 31);
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-- Execution Pipe
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ex5_ld_data :out std_ulogic_vector(0 to 255); -- EX5 Load Data Coming out of L1 D$ Array
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ex5_ld_data_par :out std_ulogic_vector(0 to 31); -- EX5 Load Data Parity Bits
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ex6_par_chk_val :out std_ulogic; -- EX6 Parity Error Check is Valid
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--pervasive
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vdd :inout power_logic;
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gnd :inout power_logic;
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nclk :in clk_logic;
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sg_0 :in std_ulogic;
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func_sl_thold_0_b :in std_ulogic;
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func_sl_force :in std_ulogic;
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func_nsl_thold_0_b :in std_ulogic;
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func_nsl_force :in std_ulogic;
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d_mode_dc :in std_ulogic;
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delay_lclkr_dc :in std_ulogic;
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mpw1_dc_b :in std_ulogic;
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mpw2_dc_b :in std_ulogic;
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scan_in :in std_ulogic;
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scan_out :out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_lsu_dc_arr;
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----
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architecture xuq_lsu_dc_arr of xuq_lsu_dc_arr is
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----------------------------
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-- components
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----------------------------
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----------------------------
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-- constants
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----------------------------
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constant ex6_par_err_val_offset :natural := 0;
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constant ex5_load_op_hit_offset :natural := ex6_par_err_val_offset + 1;
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constant arr_addr_offset :natural := ex5_load_op_hit_offset + 1;
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constant arr_bw_offset :natural := arr_addr_offset + 58-(64-(dc_size-3))+1;
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constant scan_right :natural := arr_bw_offset + 32 - 1;
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----------------------------
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-- signals
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----------------------------
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signal xuop_addr :std_ulogic_vector(64-(dc_size-3) to 58);
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signal st_byte_en :std_ulogic_vector(0 to 31);
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signal rel_addr :std_ulogic_vector(64-(dc_size-3) to 58);
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signal arr_addr_d :std_ulogic_vector(64-(dc_size-3) to 58);
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signal arr_addr_q :std_ulogic_vector(64-(dc_size-3) to 58);
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signal arr_st_data :std_ulogic_vector(0 to 255);
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signal arr_parity :std_ulogic_vector(0 to 31);
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signal arr_wr_data :std_ulogic_vector(0 to 287);
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signal arr_bw_d :std_ulogic_vector(0 to 31);
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signal arr_bw_q :std_ulogic_vector(0 to 31);
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signal arr_bw_dly_d :std_ulogic_vector(0 to 31);
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signal arr_bw_dly_q :std_ulogic_vector(0 to 31);
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signal arr_rd_data :std_ulogic_vector(0 to 287);
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signal arr_ld_data :std_ulogic_vector(0 to 255);
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signal ld_arr_parity :std_ulogic_vector(0 to 31);
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signal rel_val_data :std_ulogic;
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signal ex5_load_op_hit_d :std_ulogic;
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signal ex5_load_op_hit_q :std_ulogic;
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signal ex6_par_err_val_d :std_ulogic;
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signal ex6_par_err_val_q :std_ulogic;
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signal rel3_ex3_stg_act :std_ulogic;
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signal rel4_ex4_stg_act :std_ulogic;
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signal inj_dcache_parity_b :std_ulogic;
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signal arr_rd_data64_b :std_ulogic;
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signal stickBit64 :std_ulogic;
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signal tiup :std_ulogic;
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signal siv :std_ulogic_vector(0 to scan_right);
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signal sov :std_ulogic_vector(0 to scan_right);
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begin
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Act Signals going to all Latches
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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rel3_ex3_stg_act <= rel3_stg_act or ex3_stg_act;
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rel4_ex4_stg_act <= rel4_stg_act or ex4_stg_act;
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Inputs
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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tiup <= '1';
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xuop_addr <= ex3_p_addr;
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st_byte_en <= ex3_byte_en;
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arr_parity <= ex4_parity_gen;
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rel_val_data <= ldq_rel_data_val;
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rel_addr <= ldq_rel_addr;
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arr_rd_data <= dcarr_rd_data;
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arr_st_data <= ex4_256st_data;
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ex5_load_op_hit_d <= ex4_load_hit;
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inj_dcache_parity_b <= not inj_dcache_parity;
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Select between different Operations
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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with rel_val_data select
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arr_addr_d <= xuop_addr when '0',
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rel_addr when others;
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with rel_val_data select
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arr_bw_d <= st_byte_en when '0',
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x"FFFFFFFF" when others;
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arr_bw_dly_d <= arr_bw_q;
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Array Data Fix Up
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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arr_wr_data <= arr_st_data(0 to 127) & arr_parity(0 to 15) &
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arr_st_data(128 to 255) & arr_parity(16 to 31);
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Inject Data Cache Error
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Sticking bit64 of the array when Data Cache Parity Error Inject is on
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-- Bit64 will be stuck to 1
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-- Bit64 refers to bit2 of byte0
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arr_rd_data64_b <= not arr_rd_data(64);
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stickBit64 <= not (arr_rd_data64_b and inj_dcache_parity_b);
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Array Data Select
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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arr_ld_data <= arr_rd_data(0 to 63) & stickBit64 & arr_rd_data(65 to 127) & arr_rd_data(144 to 271);
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-- Array Parity
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ld_arr_parity <= arr_rd_data(128 to 143) & arr_rd_data(272 to 287);
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-- Parity Check is Valid
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ex6_par_err_val_d <= ex5_load_op_hit_q and not ex5_stg_flush;
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Outputs
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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bw_gen : for bi in 0 to 31 generate begin
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dcarr_bw(bi+0) <= arr_bw_q(bi);
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dcarr_bw(bi+32) <= arr_bw_q(bi);
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dcarr_bw(bi+64) <= arr_bw_q(bi);
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dcarr_bw(bi+96) <= arr_bw_q(bi);
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dcarr_bw(bi+144) <= arr_bw_q(bi);
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dcarr_bw(bi+176) <= arr_bw_q(bi);
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dcarr_bw(bi+208) <= arr_bw_q(bi);
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dcarr_bw(bi+240) <= arr_bw_q(bi);
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-- Parity Bits
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dcarr_bw(bi+128+(128*(bi/16))) <= arr_bw_q(bi);
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end generate bw_gen;
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dcarr_addr <= arr_addr_q;
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dcarr_wr_data <= arr_wr_data;
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dcarr_bw_dly <= arr_bw_dly_q;
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ex5_ld_data <= arr_ld_data;
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ex5_ld_data_par <= ld_arr_parity;
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ex6_par_chk_val <= ex6_par_err_val_q;
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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-- Registers
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-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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ex6_par_err_val_reg: tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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forcee => func_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ex6_par_err_val_offset),
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scout => sov(ex6_par_err_val_offset),
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din => ex6_par_err_val_d,
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dout => ex6_par_err_val_q);
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ex5_load_op_hit_reg: tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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forcee => func_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(ex5_load_op_hit_offset),
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scout => sov(ex5_load_op_hit_offset),
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din => ex5_load_op_hit_d,
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dout => ex5_load_op_hit_q);
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arr_addr_reg: tri_rlmreg_p
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generic map (width => 58-(64-(dc_size-3))+1, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => rel3_ex3_stg_act,
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forcee => func_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(arr_addr_offset to arr_addr_offset + arr_addr_d'length-1),
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scout => sov(arr_addr_offset to arr_addr_offset + arr_addr_d'length-1),
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din => arr_addr_d,
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dout => arr_addr_q);
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arr_bw_reg: tri_rlmreg_p
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generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => rel3_ex3_stg_act,
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forcee => func_sl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(arr_bw_offset to arr_bw_offset + arr_bw_d'length-1),
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scout => sov(arr_bw_offset to arr_bw_offset + arr_bw_d'length-1),
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din => arr_bw_d,
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dout => arr_bw_q);
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arr_bw_dly_reg: tri_regk
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generic map (width => 32, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => rel4_ex4_stg_act,
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forcee => func_nsl_force,
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d_mode => d_mode_dc,
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delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b,
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mpw2_b => mpw2_dc_b,
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thold_b => func_nsl_thold_0_b,
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din => arr_bw_dly_d,
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dout => arr_bw_dly_q);
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siv(0 to scan_right) <= sov(1 to scan_right) & scan_in;
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scan_out <= sov(0);
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end xuq_lsu_dc_arr;
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