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417 lines
21 KiB
VHDL
417 lines
21 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU Performance Event Muxing
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--
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library ieee,ibm,support,work,tri,clib;
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use ieee.std_logic_1164.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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entity xuq_perf is
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generic(
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expand_type : integer := 2);
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port(
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-- Clocks
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nclk : in clk_logic;
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-- Pervasive
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func_sl_thold_2 : in std_ulogic;
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sg_2 : in std_ulogic;
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clkoff_dc_b : in std_ulogic;
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d_mode_dc : in std_ulogic;
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delay_lclkr_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic;
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mpw2_dc_b : in std_ulogic;
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pc_xu_ccflush_dc : in std_ulogic;
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scan_in : in std_ulogic;
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scan_out : out std_ulogic;
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-- Event Inputs
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cpl_perf_tx_events : in std_ulogic_vector(0 to 75);
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spr_perf_tx_events : in std_ulogic_vector(0 to 31);
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byp_perf_tx_events : in std_ulogic_vector(0 to 11);
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fxa_perf_muldiv_in_use : in std_ulogic;
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-- PC Control Interface
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pc_xu_event_bus_enable : in std_ulogic;
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pc_xu_event_count_mode : in std_ulogic_vector(0 to 2);
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pc_xu_event_mux_ctrls : in std_ulogic_vector(0 to 47);
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-- Perf Event Output
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xu_pc_event_data : out std_ulogic_vector(0 to 7);
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-- SPR Bits
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spr_msr_gs : in std_ulogic_vector(0 to 3);
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spr_msr_pr : in std_ulogic_vector(0 to 3);
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-- Power
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vdd : inout power_logic;
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gnd : inout power_logic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_perf;
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architecture xuq_perf of xuq_perf is
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-- Latches
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signal event_en_q, event_en_d : std_ulogic_vector(0 to 3);
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signal event_data_q, event_data_d : std_ulogic_vector(xu_pc_event_data'range);
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signal event_mux_ctrls_q, event_mux_ctrls_d : std_ulogic_vector(0 to 47);
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signal cpl_perf_tx_events_q : std_ulogic_vector(0 to 75); -- input=>cpl_perf_tx_events
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signal spr_perf_tx_events_q : std_ulogic_vector(0 to 31); -- input=>spr_perf_tx_events
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signal byp_perf_tx_events_q : std_ulogic_vector(0 to 11); -- input=>byp_perf_tx_events
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signal muldiv_in_use_q : std_ulogic; -- input=>fxa_perf_muldiv_in_use
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signal processor_busy_q, processor_busy_d : std_ulogic;
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signal br_commit_q, br_commit_d : std_ulogic; -- act=>pc_event_bus_enable_q
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signal br_mispred_q, br_mispred_d : std_ulogic; -- act=>pc_event_bus_enable_q
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signal br_ta_mispred_q, br_ta_mispred_d : std_ulogic; -- act=>pc_event_bus_enable_q
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signal pc_event_count_mode_q : std_ulogic_vector(0 to 2); -- input=>pc_xu_event_count_mode
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signal pc_event_bus_enable_q : std_ulogic;
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-- Scanchains
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constant event_en_offset : integer := 0;
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constant event_data_offset : integer := event_en_offset + event_en_q'length;
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constant event_mux_ctrls_offset : integer := event_data_offset + event_data_q'length;
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constant cpl_perf_tx_events_offset : integer := event_mux_ctrls_offset + event_mux_ctrls_q'length;
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constant spr_perf_tx_events_offset : integer := cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length;
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constant byp_perf_tx_events_offset : integer := spr_perf_tx_events_offset + spr_perf_tx_events_q'length;
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constant muldiv_in_use_offset : integer := byp_perf_tx_events_offset + byp_perf_tx_events_q'length;
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constant processor_busy_offset : integer := muldiv_in_use_offset + 1;
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constant br_commit_offset : integer := processor_busy_offset + 1;
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constant br_mispred_offset : integer := br_commit_offset + 1;
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constant br_ta_mispred_offset : integer := br_mispred_offset + 1;
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constant pc_event_count_mode_offset : integer := br_ta_mispred_offset + 1;
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constant pc_event_bus_enable_offset : integer := pc_event_count_mode_offset + pc_event_count_mode_q'length;
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constant scan_right : integer := pc_event_bus_enable_offset + 1;
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signal siv : std_ulogic_vector(0 to scan_right-1);
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signal sov : std_ulogic_vector(0 to scan_right-1);
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-- Signals
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signal tiup : std_ulogic;
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signal func_sl_thold_1 : std_ulogic;
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signal sg_1 : std_ulogic;
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signal func_sl_thold_0 : std_ulogic;
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signal sg_0 : std_ulogic;
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signal func_sl_force : std_ulogic;
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signal func_sl_thold_0_b : std_ulogic;
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signal t0_events, t0_events_in : std_ulogic_vector(0 to 31);
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signal t1_events, t1_events_in : std_ulogic_vector(0 to 31);
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signal t2_events, t2_events_in : std_ulogic_vector(0 to 31);
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signal t3_events, t3_events_in : std_ulogic_vector(0 to 31);
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begin
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tiup <= '1';
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-- Processor Busy / Br Commit / Br Mispred / Br TA Mispred
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------------------------------------------ SPR
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-- Thread Running
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-- TB Tick
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-- SPR read
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-- SPR write
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-- Cycles Stalled on waitrsv
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-- External Int Asserted
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-- Critical Ext Int Asserted
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-- Perf Mon Int Asserted
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------------------------------------------ CPL
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-- PPE Commit
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-- Integer Commit
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-- uCode Commit
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-- Any Flush
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-- Branch Commit
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-- Branch Mispredict Commit
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-- Branch Taken Commit
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-- Branch TA Mispredict Commit
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-- Mult/Div collision
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-- External Interrupt Pending
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-- Critical External Interrupt Pending
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-- Performance Mon Interrupt Pending
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-- Opcode Match
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-- Concurrent Run Instructions
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-- External, Critical, Perf Interrupts Taken (any thread)
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-- External Interrupt Taken
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-- Critical External Interrupt Taken
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-- Performance Mon Interrupt Taken
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-- Processor Doorbell or Critical Doorbell Taken
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------------------------------------------ BYP
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-- STCX Fail
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-- icswx failed
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-- icswx finished
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------------------------------------------ DEC
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-- Mult/Div Busy
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processor_busy_d <= spr_perf_tx_events_q(00) or spr_perf_tx_events_q(08) or spr_perf_tx_events_q(16) or spr_perf_tx_events_q(24);
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br_commit_d <= cpl_perf_tx_events_q(04) or cpl_perf_tx_events_q(04+19) or cpl_perf_tx_events_q(04+38) or cpl_perf_tx_events_q(04+57);
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br_mispred_d <= cpl_perf_tx_events_q(05) or cpl_perf_tx_events_q(05+19) or cpl_perf_tx_events_q(05+38) or cpl_perf_tx_events_q(05+57);
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br_ta_mispred_d <= cpl_perf_tx_events_q(07) or cpl_perf_tx_events_q(07+19) or cpl_perf_tx_events_q(07+38) or cpl_perf_tx_events_q(07+57);
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t0_events_in <= processor_busy_q & spr_perf_tx_events_q(00 to 07) & cpl_perf_tx_events_q(00 to 18) & byp_perf_tx_events_q(00 to 02) & muldiv_in_use_q;
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t1_events_in <= br_commit_q & spr_perf_tx_events_q(08 to 15) & cpl_perf_tx_events_q(19 to 37) & byp_perf_tx_events_q(03 to 05) & muldiv_in_use_q;
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t2_events_in <= br_mispred_q & spr_perf_tx_events_q(16 to 23) & cpl_perf_tx_events_q(38 to 56) & byp_perf_tx_events_q(06 to 08) & muldiv_in_use_q;
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t3_events_in <= br_ta_mispred_q & spr_perf_tx_events_q(24 to 31) & cpl_perf_tx_events_q(57 to 75) & byp_perf_tx_events_q(09 to 11) & muldiv_in_use_q;
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t0_events <= t0_events_in and (0 to 31=>event_en_q(0));
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t1_events <= t1_events_in and (0 to 31=>event_en_q(1));
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t2_events <= t2_events_in and (0 to 31=>event_en_q(2));
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t3_events <= t3_events_in and (0 to 31=>event_en_q(3));
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xu_pc_event_data <= event_data_q;
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event_mux_ctrls_d <= pc_xu_event_mux_ctrls;
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event_en_d <= ( spr_msr_pr and (0 to 3=>pc_event_count_mode_q(0))) or -- User
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(not spr_msr_pr and spr_msr_gs and (0 to 3=>pc_event_count_mode_q(1))) or -- Guest Supervisor
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(not spr_msr_pr and not spr_msr_gs and (0 to 3=>pc_event_count_mode_q(2))); -- Hypervisor
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xuq_perf_mux1 : entity clib.c_event_mux(c_event_mux)
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generic map(events_in => 128)
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port map(
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vd => vdd,
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gd => gnd,
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t0_events => t0_events,
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t1_events => t1_events,
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t2_events => t2_events,
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t3_events => t3_events,
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select_bits => event_mux_ctrls_q,
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event_bits => event_data_d
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);
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-- Latch Instances
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event_en_latch : tri_rlmreg_p
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generic map (width => event_en_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(event_en_offset to event_en_offset + event_en_q'length-1),
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scout => sov(event_en_offset to event_en_offset + event_en_q'length-1),
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din => event_en_d,
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dout => event_en_q);
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event_data_latch : tri_rlmreg_p
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generic map (width => event_data_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(event_data_offset to event_data_offset + event_data_q'length-1),
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scout => sov(event_data_offset to event_data_offset + event_data_q'length-1),
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din => event_data_d,
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dout => event_data_q);
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event_mux_ctrls_latch : tri_rlmreg_p
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generic map (width => event_mux_ctrls_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1),
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scout => sov(event_mux_ctrls_offset to event_mux_ctrls_offset + event_mux_ctrls_q'length-1),
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din => event_mux_ctrls_d,
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dout => event_mux_ctrls_q);
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cpl_perf_tx_events_latch : tri_rlmreg_p
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generic map (width => cpl_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(cpl_perf_tx_events_offset to cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length-1),
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scout => sov(cpl_perf_tx_events_offset to cpl_perf_tx_events_offset + cpl_perf_tx_events_q'length-1),
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din => cpl_perf_tx_events,
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dout => cpl_perf_tx_events_q);
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spr_perf_tx_events_latch : tri_rlmreg_p
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generic map (width => spr_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(spr_perf_tx_events_offset to spr_perf_tx_events_offset + spr_perf_tx_events_q'length-1),
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scout => sov(spr_perf_tx_events_offset to spr_perf_tx_events_offset + spr_perf_tx_events_q'length-1),
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din => spr_perf_tx_events,
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dout => spr_perf_tx_events_q);
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byp_perf_tx_events_latch : tri_rlmreg_p
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generic map (width => byp_perf_tx_events_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(byp_perf_tx_events_offset to byp_perf_tx_events_offset + byp_perf_tx_events_q'length-1),
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scout => sov(byp_perf_tx_events_offset to byp_perf_tx_events_offset + byp_perf_tx_events_q'length-1),
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din => byp_perf_tx_events,
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dout => byp_perf_tx_events_q);
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muldiv_in_use_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(muldiv_in_use_offset),
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scout => sov(muldiv_in_use_offset),
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din => fxa_perf_muldiv_in_use,
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dout => muldiv_in_use_q);
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processor_busy_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(processor_busy_offset),
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scout => sov(processor_busy_offset),
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din => processor_busy_d,
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dout => processor_busy_q);
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br_commit_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(br_commit_offset),
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scout => sov(br_commit_offset),
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din => br_commit_d,
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dout => br_commit_q);
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br_mispred_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(br_mispred_offset),
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scout => sov(br_mispred_offset),
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din => br_mispred_d,
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dout => br_mispred_q);
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br_ta_mispred_latch : tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
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scin => siv(br_ta_mispred_offset),
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scout => sov(br_ta_mispred_offset),
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din => br_ta_mispred_d,
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dout => br_ta_mispred_q);
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pc_event_count_mode_latch : tri_rlmreg_p
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generic map (width => pc_event_count_mode_q'length, init => 0, expand_type => expand_type, needs_sreset => 1)
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port map (nclk => nclk, vd => vdd, gd => gnd,
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act => pc_event_bus_enable_q,
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forcee => func_sl_force,
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d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
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mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
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thold_b => func_sl_thold_0_b,
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sg => sg_0,
|
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scin => siv(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1),
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|
scout => sov(pc_event_count_mode_offset to pc_event_count_mode_offset + pc_event_count_mode_q'length-1),
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din => pc_xu_event_count_mode,
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|
dout => pc_event_count_mode_q);
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pc_event_bus_enable_latch : tri_rlmlatch_p
|
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generic map (init => 0, expand_type => expand_type, needs_sreset => 1)
|
|
port map (nclk => nclk, vd => vdd, gd => gnd,
|
|
act => tiup,
|
|
forcee => func_sl_force,
|
|
d_mode => d_mode_dc, delay_lclkr => delay_lclkr_dc,
|
|
mpw1_b => mpw1_dc_b, mpw2_b => mpw2_dc_b,
|
|
thold_b => func_sl_thold_0_b,
|
|
sg => sg_0,
|
|
scin => siv(pc_event_bus_enable_offset),
|
|
scout => sov(pc_event_bus_enable_offset),
|
|
din => pc_xu_event_bus_enable,
|
|
dout => pc_event_bus_enable_q);
|
|
|
|
-------------------------------------------------
|
|
-- Pervasive
|
|
-------------------------------------------------
|
|
perv_2to1_reg: tri_plat
|
|
generic map (width => 2, expand_type => expand_type)
|
|
port map (vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
flush => pc_xu_ccflush_dc,
|
|
din(0) => func_sl_thold_2,
|
|
din(1) => sg_2,
|
|
q(0) => func_sl_thold_1,
|
|
q(1) => sg_1);
|
|
|
|
perv_1to0_reg: tri_plat
|
|
generic map (width => 2, expand_type => expand_type)
|
|
port map (vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
flush => pc_xu_ccflush_dc,
|
|
din(0) => func_sl_thold_1,
|
|
din(1) => sg_1,
|
|
q(0) => func_sl_thold_0,
|
|
q(1) => sg_0);
|
|
|
|
perv_lcbor_func_sl: tri_lcbor
|
|
generic map (expand_type => expand_type)
|
|
port map (clkoff_b => clkoff_dc_b,
|
|
thold => func_sl_thold_0,
|
|
sg => sg_0,
|
|
act_dis => '0',
|
|
forcee => func_sl_force,
|
|
thold_b => func_sl_thold_0_b);
|
|
|
|
|
|
siv(0 to siv'right) <= sov(1 to siv'right) & scan_in;
|
|
scan_out <= sov(0);
|
|
|
|
end architecture xuq_perf;
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