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398 lines
17 KiB
VHDL
398 lines
17 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU Pervasive
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--
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use work.xuq_pkg.all;
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entity xuq_perv is
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generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
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port(
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vdd : inout power_logic;
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gnd : inout power_logic;
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nclk : in clk_logic;
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an_ac_scan_dis_dc_b : in std_ulogic;
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pc_xu_sg_3 : in std_ulogic_vector(0 to 4);
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pc_xu_func_sl_thold_3 : in std_ulogic_vector(0 to 4);
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pc_xu_func_slp_sl_thold_3 : in std_ulogic_vector(0 to 4);
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pc_xu_func_nsl_thold_3 : in std_ulogic;
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pc_xu_func_slp_nsl_thold_3 : in std_ulogic;
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pc_xu_gptr_sl_thold_3 : in std_ulogic;
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pc_xu_abst_sl_thold_3 : in std_ulogic;
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pc_xu_abst_slp_sl_thold_3 : in std_ulogic;
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pc_xu_regf_sl_thold_3 : in std_ulogic;
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pc_xu_regf_slp_sl_thold_3 : in std_ulogic;
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pc_xu_time_sl_thold_3 : in std_ulogic;
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pc_xu_cfg_sl_thold_3 : in std_ulogic;
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pc_xu_cfg_slp_sl_thold_3 : in std_ulogic;
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pc_xu_ary_nsl_thold_3 : in std_ulogic;
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pc_xu_ary_slp_nsl_thold_3 : in std_ulogic;
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pc_xu_repr_sl_thold_3 : in std_ulogic;
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pc_xu_bolt_sl_thold_3 : in std_ulogic;
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pc_xu_bo_enable_3 : in std_ulogic;
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pc_xu_fce_3 : in std_ulogic_vector(0 to 1);
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pc_xu_ccflush_dc : in std_ulogic;
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an_ac_scan_diag_dc : in std_ulogic;
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sg_2 : out std_ulogic_vector(0 to 3);
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fce_2 : out std_ulogic_vector(0 to 1);
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func_sl_thold_2 : out std_ulogic_vector(0 to 3);
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func_slp_sl_thold_2 : out std_ulogic_vector(0 to 1);
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func_nsl_thold_2 : out std_ulogic;
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func_slp_nsl_thold_2 : out std_ulogic;
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abst_sl_thold_2 : out std_ulogic;
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abst_slp_sl_thold_2 : out std_ulogic;
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regf_sl_thold_2 : out std_ulogic;
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regf_slp_sl_thold_2 : out std_ulogic;
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time_sl_thold_2 : out std_ulogic;
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gptr_sl_thold_2 : out std_ulogic;
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ary_nsl_thold_2 : out std_ulogic;
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ary_slp_nsl_thold_2 : out std_ulogic;
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repr_sl_thold_2 : out std_ulogic;
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cfg_sl_thold_2 : out std_ulogic;
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cfg_slp_sl_thold_2 : out std_ulogic;
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bolt_sl_thold_2 : out std_ulogic;
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bo_enable_2 : out std_ulogic;
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sg_0 : out std_ulogic;
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sg_1 : out std_ulogic;
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ary_nsl_thold_0 : out std_ulogic;
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abst_sl_thold_0 : out std_ulogic;
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time_sl_thold_0 : out std_ulogic;
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repr_sl_thold_0 : out std_ulogic;
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clkoff_dc_b : out std_ulogic;
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d_mode_dc : out std_ulogic;
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delay_lclkr_dc : out std_ulogic_vector(0 to 4);
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mpw1_dc_b : out std_ulogic_vector(0 to 4);
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mpw2_dc_b : out std_ulogic;
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g6t_clkoff_dc_b : out std_ulogic;
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g6t_d_mode_dc : out std_ulogic;
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g6t_delay_lclkr_dc : out std_ulogic_vector(0 to 4);
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g6t_mpw1_dc_b : out std_ulogic_vector(0 to 4);
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g6t_mpw2_dc_b : out std_ulogic;
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g8t_clkoff_dc_b : out std_ulogic;
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g8t_d_mode_dc : out std_ulogic;
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g8t_delay_lclkr_dc : out std_ulogic_vector(0 to 4);
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g8t_mpw1_dc_b : out std_ulogic_vector(0 to 4);
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g8t_mpw2_dc_b : out std_ulogic;
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cam_clkoff_dc_b : out std_ulogic;
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cam_d_mode_dc : out std_ulogic;
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cam_delay_lclkr_dc : out std_ulogic_vector(0 to 4);
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cam_act_dis_dc : out std_ulogic;
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cam_mpw1_dc_b : out std_ulogic_vector(0 to 4);
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cam_mpw2_dc_b : out std_ulogic;
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gptr_scan_in : in std_ulogic;
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gptr_scan_out : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_perv;
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architecture xuq_perv of xuq_perv is
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signal gptr_sov, gptr_siv : std_ulogic_vector(0 to 3);
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signal perv_sg_2 : std_ulogic_vector(0 to 3);
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signal perv_sg_2_b : std_ulogic_vector(0 to 3);
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signal gptr_sl_thold_2_int : std_ulogic;
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signal gptr_sl_thold_2_int_b : std_ulogic;
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signal gptr_sl_thold_1, sg_1_int : std_ulogic;
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signal gptr_sl_thold_0, sg_0_int : std_ulogic;
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signal time_sl_thold_0_int : std_ulogic;
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signal ary_nsl_thold_2_int : std_ulogic;
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signal ary_nsl_thold_2_int_b : std_ulogic;
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signal ary_slp_nsl_thold_2_int : std_ulogic;
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signal abst_sl_thold_2_int : std_ulogic;
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signal abst_sl_thold_2_int_b : std_ulogic;
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signal abst_slp_sl_thold_2_int : std_ulogic;
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signal regf_sl_thold_2_int : std_ulogic;
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signal regf_slp_sl_thold_2_int : std_ulogic;
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signal func_slp_nsl_thold_2_int : std_ulogic;
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signal time_sl_thold_2_int : std_ulogic;
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signal time_sl_thold_2_int_b : std_ulogic;
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signal repr_sl_thold_2_int : std_ulogic;
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signal repr_sl_thold_2_int_b : std_ulogic;
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signal ary_nsl_thold_1 : std_ulogic;
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signal abst_sl_thold_1 : std_ulogic;
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signal time_sl_thold_1 : std_ulogic;
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signal repr_sl_thold_1 : std_ulogic;
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signal func_sl_thold_2_int : std_ulogic_vector(0 to 3);
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signal bolt_sl_thold_2_int : std_ulogic;
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signal bo_enable_2_int : std_ulogic;
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signal fce_2_int : std_ulogic_vector(0 to 1);
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signal func_slp_sl_thold_2_int : std_ulogic_vector(0 to 1);
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signal cfg_sl_thold_2_int : std_ulogic;
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signal cfg_slp_sl_thold_2_int : std_ulogic;
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signal func_nsl_thold_2_int : std_ulogic;
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signal clkoff_dc_b_int : std_ulogic;
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signal d_mode_dc_int : std_ulogic;
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signal delay_lclkr_dc_int : std_ulogic_vector(0 to 4);
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signal mpw1_dc_b_int : std_ulogic_vector(0 to 4);
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signal mpw2_dc_b_int : std_ulogic;
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signal g6t_clkoff_dc_b_int : std_ulogic;
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signal g6t_d_mode_dc_int : std_ulogic;
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signal g6t_delay_lclkr_dc_int : std_ulogic_vector(0 to 4);
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signal g6t_mpw1_dc_b_int : std_ulogic_vector(0 to 4);
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signal g6t_mpw2_dc_b_int : std_ulogic;
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signal g8t_clkoff_dc_b_int : std_ulogic;
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signal g8t_d_mode_dc_int : std_ulogic;
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signal g8t_delay_lclkr_dc_int : std_ulogic_vector(0 to 4);
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signal g8t_mpw1_dc_b_int : std_ulogic_vector(0 to 4);
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signal g8t_mpw2_dc_b_int : std_ulogic;
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signal cam_clkoff_dc_b_int : std_ulogic;
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signal cam_d_mode_dc_int : std_ulogic;
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signal cam_delay_lclkr_dc_int : std_ulogic_vector(0 to 4);
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signal cam_mpw1_dc_b_int : std_ulogic_vector(0 to 4);
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signal cam_mpw2_dc_b_int : std_ulogic;
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begin
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perv_3to2_reg: tri_plat
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generic map (width => 27, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_xu_ccflush_dc,
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din(0 to 3) => pc_xu_func_sl_thold_3(0 to 3),
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din(4 to 5) => pc_xu_func_slp_sl_thold_3(0 to 1),
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din(6) => pc_xu_gptr_sl_thold_3,
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din(7 to 10) => pc_xu_sg_3(0 to 3),
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din(11 to 12) => pc_xu_fce_3(0 to 1),
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din(13) => pc_xu_func_nsl_thold_3,
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din(14) => pc_xu_abst_sl_thold_3,
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din(15) => pc_xu_abst_slp_sl_thold_3,
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din(16) => pc_xu_time_sl_thold_3,
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din(17) => pc_xu_ary_nsl_thold_3,
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din(18) => pc_xu_ary_slp_nsl_thold_3,
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din(19) => pc_xu_cfg_sl_thold_3,
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din(20) => pc_xu_cfg_slp_sl_thold_3,
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din(21) => pc_xu_repr_sl_thold_3,
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din(22) => pc_xu_regf_sl_thold_3,
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din(23) => pc_xu_regf_slp_sl_thold_3,
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din(24) => pc_xu_func_slp_nsl_thold_3,
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din(25) => pc_xu_bolt_sl_thold_3,
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din(26) => pc_xu_bo_enable_3,
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q(0 to 3) => func_sl_thold_2_int(0 to 3),
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q(4 to 5) => func_slp_sl_thold_2_int(0 to 1),
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q(6) => gptr_sl_thold_2_int,
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q(7 to 10) => perv_sg_2(0 to 3),
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q(11 to 12) => fce_2_int(0 to 1),
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q(13) => func_nsl_thold_2_int,
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q(14) => abst_sl_thold_2_int,
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q(15) => abst_slp_sl_thold_2_int,
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q(16) => time_sl_thold_2_int,
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q(17) => ary_nsl_thold_2_int,
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q(18) => ary_slp_nsl_thold_2_int,
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q(19) => cfg_sl_thold_2_int,
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q(20) => cfg_slp_sl_thold_2_int,
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q(21) => repr_sl_thold_2_int,
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q(22) => regf_sl_thold_2_int,
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q(23) => regf_slp_sl_thold_2_int,
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q(24) => func_slp_nsl_thold_2_int,
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q(25) => bolt_sl_thold_2_int,
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q(26) => bo_enable_2_int);
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sg_2 <= perv_sg_2;
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perv_sg_2_b <= perv_sg_2;
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sg_1 <= sg_1_int;
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sg_0 <= sg_0_int;
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ary_nsl_thold_2 <= ary_nsl_thold_2_int;
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ary_nsl_thold_2_int_b<= ary_nsl_thold_2_int;
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ary_slp_nsl_thold_2 <= ary_slp_nsl_thold_2_int;
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abst_sl_thold_2 <= abst_sl_thold_2_int;
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abst_sl_thold_2_int_b <= abst_sl_thold_2_int;
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abst_slp_sl_thold_2 <= abst_slp_sl_thold_2_int;
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regf_sl_thold_2 <= regf_sl_thold_2_int;
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regf_slp_sl_thold_2 <= regf_slp_sl_thold_2_int;
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time_sl_thold_2 <= time_sl_thold_2_int;
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time_sl_thold_2_int_b <= time_sl_thold_2_int;
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repr_sl_thold_2 <= repr_sl_thold_2_int;
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repr_sl_thold_2_int_b <= repr_sl_thold_2_int;
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func_sl_thold_2 <= func_sl_thold_2_int;
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bolt_sl_thold_2 <= bolt_sl_thold_2_int;
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bo_enable_2 <= bo_enable_2_int;
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fce_2 <= fce_2_int;
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func_slp_sl_thold_2 <= func_slp_sl_thold_2_int;
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cfg_sl_thold_2 <= cfg_sl_thold_2_int;
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cfg_slp_sl_thold_2 <= cfg_slp_sl_thold_2_int;
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func_nsl_thold_2 <= func_nsl_thold_2_int;
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func_slp_nsl_thold_2 <= func_slp_nsl_thold_2_int;
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clkoff_dc_b <= clkoff_dc_b_int;
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d_mode_dc <= d_mode_dc_int;
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delay_lclkr_dc <= delay_lclkr_dc_int;
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mpw1_dc_b <= mpw1_dc_b_int;
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mpw2_dc_b <= mpw2_dc_b_int;
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time_sl_thold_0 <= time_sl_thold_0_int;
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g6t_clkoff_dc_b <= g6t_clkoff_dc_b_int;
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g6t_d_mode_dc <= g6t_d_mode_dc_int;
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g6t_delay_lclkr_dc <= g6t_delay_lclkr_dc_int;
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g6t_mpw1_dc_b <= g6t_mpw1_dc_b_int;
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g6t_mpw2_dc_b <= g6t_mpw2_dc_b_int;
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g8t_clkoff_dc_b <= g8t_clkoff_dc_b_int;
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g8t_d_mode_dc <= g8t_d_mode_dc_int;
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g8t_delay_lclkr_dc <= g8t_delay_lclkr_dc_int;
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g8t_mpw1_dc_b <= g8t_mpw1_dc_b_int;
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g8t_mpw2_dc_b <= g8t_mpw2_dc_b_int;
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cam_clkoff_dc_b <= cam_clkoff_dc_b_int;
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cam_delay_lclkr_dc <= cam_delay_lclkr_dc_int;
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cam_act_dis_dc <= '0';
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cam_d_mode_dc <= cam_d_mode_dc_int;
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cam_mpw1_dc_b <= cam_mpw1_dc_b_int;
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cam_mpw2_dc_b <= cam_mpw2_dc_b_int;
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gptr_sl_thold_2 <= gptr_sl_thold_2_int;
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gptr_sl_thold_2_int_b <= gptr_sl_thold_2_int;
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perv_2to1_reg: tri_plat
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generic map (width => 6, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_xu_ccflush_dc,
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din(0) => gptr_sl_thold_2_int_b,
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din(1) => perv_sg_2_b(0),
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din(2) => ary_nsl_thold_2_int_b,
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din(3) => abst_sl_thold_2_int_b,
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din(4) => time_sl_thold_2_int_b,
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din(5) => repr_sl_thold_2_int_b,
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q(0) => gptr_sl_thold_1,
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q(1) => sg_1_int,
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q(2) => ary_nsl_thold_1,
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q(3) => abst_sl_thold_1,
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q(4) => time_sl_thold_1,
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q(5) => repr_sl_thold_1);
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perv_1to0_reg: tri_plat
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generic map (width => 6, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => pc_xu_ccflush_dc,
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din(0) => gptr_sl_thold_1,
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din(1) => sg_1_int,
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din(2) => ary_nsl_thold_1,
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din(3) => abst_sl_thold_1,
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din(4) => time_sl_thold_1,
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din(5) => repr_sl_thold_1,
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q(0) => gptr_sl_thold_0,
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q(1) => sg_0_int,
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q(2) => ary_nsl_thold_0,
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q(3) => abst_sl_thold_0,
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q(4) => time_sl_thold_0_int,
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q(5) => repr_sl_thold_0);
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perv_lcbctrl_0: tri_lcbcntl_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => sg_0_int,
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nclk => nclk,
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scan_in => gptr_siv(3),
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scan_diag_dc => an_ac_scan_diag_dc,
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thold => gptr_sl_thold_0,
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clkoff_dc_b => clkoff_dc_b_int,
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delay_lclkr_dc => delay_lclkr_dc_int(0 to 4),
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act_dis_dc => open,
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d_mode_dc => d_mode_dc_int,
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mpw1_dc_b => mpw1_dc_b_int(0 to 4),
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mpw2_dc_b => mpw2_dc_b_int,
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scan_out => gptr_sov(3));
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perv_lcbctrl_g6t_0: tri_lcbcntl_array_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => sg_0_int,
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nclk => nclk,
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scan_in => gptr_siv(0),
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scan_diag_dc => an_ac_scan_diag_dc,
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thold => gptr_sl_thold_0,
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clkoff_dc_b => g6t_clkoff_dc_b_int,
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delay_lclkr_dc => g6t_delay_lclkr_dc_int(0 to 4),
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act_dis_dc => open,
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d_mode_dc => g6t_d_mode_dc_int,
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mpw1_dc_b => g6t_mpw1_dc_b_int(0 to 4),
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mpw2_dc_b => g6t_mpw2_dc_b_int,
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scan_out => gptr_sov(0));
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perv_lcbctrl_g8t_0: tri_lcbcntl_array_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => sg_0_int,
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nclk => nclk,
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scan_in => gptr_siv(1),
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scan_diag_dc => an_ac_scan_diag_dc,
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thold => gptr_sl_thold_0,
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clkoff_dc_b => g8t_clkoff_dc_b_int,
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delay_lclkr_dc => g8t_delay_lclkr_dc_int(0 to 4),
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act_dis_dc => open,
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d_mode_dc => g8t_d_mode_dc_int,
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mpw1_dc_b => g8t_mpw1_dc_b_int(0 to 4),
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mpw2_dc_b => g8t_mpw2_dc_b_int,
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scan_out => gptr_sov(1));
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perv_lcbctrl_cam_0: tri_lcbcntl_array_mac
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generic map (expand_type => expand_type)
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port map (
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vdd => vdd,
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gnd => gnd,
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sg => sg_0_int,
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nclk => nclk,
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scan_in => gptr_siv(2),
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scan_diag_dc => an_ac_scan_diag_dc,
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thold => gptr_sl_thold_0,
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clkoff_dc_b => cam_clkoff_dc_b_int,
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delay_lclkr_dc => cam_delay_lclkr_dc_int(0 to 4),
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act_dis_dc => open,
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d_mode_dc => cam_d_mode_dc_int,
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mpw1_dc_b => cam_mpw1_dc_b_int(0 to 4),
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mpw2_dc_b => cam_mpw2_dc_b_int,
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scan_out => gptr_sov(2));
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|
|
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gptr_siv(0 to gptr_siv'right) <= gptr_sov(1 to gptr_siv'right) & gptr_scan_in;
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gptr_scan_out <= gptr_sov(0) and an_ac_scan_dis_dc_b;
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mark_unused(pc_xu_func_sl_thold_3(4));
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mark_unused(pc_xu_func_slp_sl_thold_3(2 to 4));
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mark_unused(pc_xu_sg_3(4));
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|
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end xuq_perv;
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