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83 lines
3.4 KiB
VHDL
83 lines
3.4 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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-- Description: XU SPR - DAC Enable Component
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity xuq_spr_dacen is
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generic(
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threads : integer := 4);
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port(
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spr_msr_pr : in std_ulogic_vector(0 to threads-1);
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spr_msr_ds : in std_ulogic_vector(0 to threads-1);
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spr_dbcr0_dac : in std_ulogic_vector(0 to 2*threads-1);
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spr_dbcr_dac_us : in std_ulogic_vector(0 to 2*threads-1);
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spr_dbcr_dac_er : in std_ulogic_vector(0 to 2*threads-1);
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val : in std_ulogic_vector(0 to threads-1);
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load : in std_ulogic;
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store : in std_ulogic;
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dacr_en : out std_ulogic_vector(0 to threads-1);
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dacw_en : out std_ulogic_vector(0 to threads-1)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_spr_dacen;
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architecture xuq_spr_dacen of xuq_spr_dacen is
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-- Signals
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signal dac_ld_en,dac_st_en : std_ulogic_vector(0 to threads-1);
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signal dac_us_en,dac_er_en : std_ulogic_vector(0 to threads-1);
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begin
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dacen_gen : for t in 0 to threads-1 generate
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dac_ld_en(t) <= spr_dbcr0_dac(0+2*t) and load;
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dac_st_en(t) <= spr_dbcr0_dac(1+2*t) and store;
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dac_us_en(t) <= (not spr_dbcr_dac_us(0+2*t) and not spr_dbcr_dac_us(1+2*t)) or
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( spr_dbcr_dac_us(0+2*t) and (spr_dbcr_dac_us(1+2*t) xnor spr_msr_pr(t)));
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dac_er_en(t) <= (not spr_dbcr_dac_er(0+2*t) and not spr_dbcr_dac_er(1+2*t)) or
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( spr_dbcr_dac_er(0+2*t) and (spr_dbcr_dac_er(1+2*t) xnor spr_msr_ds(t)));
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dacr_en(t) <= val(t) and dac_ld_en(t) and dac_us_en(t) and dac_er_en(t);
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dacw_en(t) <= val(t) and dac_st_en(t) and dac_us_en(t) and dac_er_en(t);
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end generate;
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end architecture xuq_spr_dacen;
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