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412 lines
15 KiB
VHDL
412 lines
15 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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entity tri_144x78_2r2w is
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generic(
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expand_type : integer := 1);
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port (
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vdd :inout power_logic;
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gnd :inout power_logic;
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nclk :in clk_logic;
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abist_en :in std_ulogic;
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abist_raw_dc_b :in std_ulogic;
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r0e_abist_comp_en :in std_ulogic;
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r1e_abist_comp_en :in std_ulogic;
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lbist_en :in std_ulogic;
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lcb_act_dis_dc :in std_ulogic;
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lcb_clkoff_dc_b :in std_ulogic_vector(0 to 1);
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lcb_d_mode_dc :in std_ulogic;
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lcb_delay_lclkr_dc :in std_ulogic_vector(0 to 9);
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lcb_fce_0 :in std_ulogic;
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lcb_mpw1_dc_b :in std_ulogic_vector(1 to 9);
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lcb_mpw2_dc_b :in std_ulogic;
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lcb_scan_diag_dc :in std_ulogic;
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lcb_scan_dis_dc_b :in std_ulogic;
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lcb_sg_0 :in std_ulogic;
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lcb_time_sg_0 :in std_ulogic;
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lcb_obs0_sg_0 :in std_ulogic;
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lcb_obs1_sg_0 :in std_ulogic;
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lcb_obs0_sl_thold_0 :in std_ulogic;
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lcb_obs1_sl_thold_0 :in std_ulogic;
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lcb_abst_sl_thold_0 :in std_ulogic;
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lcb_time_sl_thold_0 :in std_ulogic;
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lcb_ary_nsl_thold_0 :in std_ulogic;
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r_scan_in :in std_ulogic;
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r_scan_out :out std_ulogic;
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w_scan_in :in std_ulogic;
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w_scan_out :out std_ulogic;
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time_scan_in :in std_ulogic;
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time_scan_out :out std_ulogic;
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obs0_scan_in :in std_ulogic;
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obs0_scan_out :out std_ulogic;
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obs1_scan_in :in std_ulogic;
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obs1_scan_out :out std_ulogic;
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lcb_bolt_sl_thold_0 :in std_ulogic;
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pc_bo_enable_2 :in std_ulogic;
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pc_bo_reset :in std_ulogic;
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pc_bo_unload :in std_ulogic;
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pc_bo_load :in std_ulogic;
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pc_bo_shdata :in std_ulogic;
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pc_bo_select :in std_ulogic;
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bo_pc_failout :out std_ulogic;
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bo_pc_diagloop :out std_ulogic;
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tri_lcb_mpw1_dc_b :in std_ulogic;
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tri_lcb_mpw2_dc_b :in std_ulogic;
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tri_lcb_delay_lclkr_dc :in std_ulogic;
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tri_lcb_clkoff_dc_b :in std_ulogic;
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tri_lcb_act_dis_dc :in std_ulogic;
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r0e_act :in std_ulogic;
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r0e_en_func :in std_ulogic;
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r0e_en_abist :in std_ulogic;
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r0e_addr_func :in std_ulogic_vector(0 to 7);
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r0e_addr_abist :in std_ulogic_vector(0 to 7);
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r0e_data_out :out std_ulogic_vector(0 to 77);
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r0e_byp_e :in std_ulogic;
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r0e_byp_l :in std_ulogic;
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r0e_byp_r :in std_ulogic;
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r0e_sel_lbist :in std_ulogic;
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r1e_act :in std_ulogic;
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r1e_en_func :in std_ulogic;
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r1e_en_abist :in std_ulogic;
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r1e_addr_func :in std_ulogic_vector(0 to 7);
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r1e_addr_abist :in std_ulogic_vector(0 to 7);
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r1e_data_out :out std_ulogic_vector(0 to 77);
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r1e_byp_e :in std_ulogic;
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r1e_byp_l :in std_ulogic;
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r1e_byp_r :in std_ulogic;
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r1e_sel_lbist :in std_ulogic;
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w0e_act :in std_ulogic;
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w0e_en_func :in std_ulogic;
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w0e_en_abist :in std_ulogic;
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w0e_addr_func :in std_ulogic_vector(0 to 7);
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w0e_addr_abist :in std_ulogic_vector(0 to 7);
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w0e_data_func :in std_ulogic_vector(0 to 77);
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w0e_data_abist :in std_ulogic_vector(0 to 3);
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w0l_act :in std_ulogic;
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w0l_en_func :in std_ulogic;
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w0l_en_abist :in std_ulogic;
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w0l_addr_func :in std_ulogic_vector(0 to 7);
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w0l_addr_abist :in std_ulogic_vector(0 to 7);
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w0l_data_func :in std_ulogic_vector(0 to 77);
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w0l_data_abist :in std_ulogic_vector(0 to 3) );
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-- synopsys translate_off
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-- synopsys translate_on
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end entity tri_144x78_2r2w;
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architecture tri_144x78_2r2w of tri_144x78_2r2w is
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begin
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a : if expand_type = 1 generate
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component RAMB16_S36_S36
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-- pragma translate_off
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generic(
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SIM_COLLISION_CHECK : string := "none");
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-- pragma translate_on
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port(
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DOA : out std_logic_vector(31 downto 0);
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DOB : out std_logic_vector(31 downto 0);
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DOPA : out std_logic_vector(3 downto 0);
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DOPB : out std_logic_vector(3 downto 0);
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ADDRA : in std_logic_vector(8 downto 0);
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ADDRB : in std_logic_vector(8 downto 0);
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector(31 downto 0);
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DIB : in std_logic_vector(31 downto 0);
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DIPA : in std_logic_vector(3 downto 0);
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DIPB : in std_logic_vector(3 downto 0);
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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SSRA : in std_ulogic;
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SSRB : in std_ulogic;
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WEA : in std_ulogic;
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WEB : in std_ulogic);
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end component;
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-- pragma translate_off
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-- pragma translate_on
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signal tilo : std_ulogic;
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signal tihi : std_ulogic;
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signal zeross : std_logic_vector(0 to 3);
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signal correct_clk : std_ulogic;
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signal clk2x : std_ulogic;
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signal reset : std_ulogic;
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signal reset_hi : std_ulogic;
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signal reset_lo : std_ulogic;
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signal reset_q : std_ulogic;
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signal sinit0_q : std_logic;
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signal sinit1_q : std_logic;
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signal flipper_d : std_ulogic;
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signal flipper_q : std_ulogic;
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signal doutb0 : std_logic_vector(0 to 77);
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signal doutb0_q : std_ulogic_vector(0 to 77);
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signal dinfa0_par : std_logic_vector(64 to 95);
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signal doutb0_par : std_logic_vector(64 to 95);
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signal weaf : std_logic;
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signal addra : std_logic_vector(0 to 8);
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signal addrb0 : std_logic_vector(0 to 8);
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signal dinfa : std_logic_vector(0 to 77);
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signal dinfb : std_logic_vector(0 to 31);
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signal w0e_data_q : std_ulogic_vector(0 to 77);
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signal w0l_data_q : std_ulogic_vector(0 to 77);
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signal w0l_en_q : std_ulogic;
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signal w0l_addr_q : std_ulogic_vector(0 to 7);
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signal r1e_addr_q : std_ulogic_vector(0 to 7);
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signal r0e_byp_e_q : std_ulogic;
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signal r0e_byp_l_q : std_ulogic;
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signal r1e_byp_e_q : std_ulogic;
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signal r1e_byp_l_q : std_ulogic;
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signal r0_byp_sel : std_ulogic_vector(0 to 1);
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signal r1_byp_sel : std_ulogic_vector(0 to 1);
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signal unused : std_ulogic;
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-- synopsys translate_off
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-- synopsys translate_on
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begin
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tilo <= '0';
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tihi <= '1';
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zeross <= (0 to 3 => '0');
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reset <= nclk.sreset;
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correct_clk <= nclk.clk;
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clk2x <= nclk.clk2x;
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reset_hi <= reset;
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reset_lo <= not reset_q after 1 ns ;
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flipper_d <= not flipper_q;
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slatch: process (correct_clk,reset) begin
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if rising_edge(correct_clk) then
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if (reset = '1') then
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w0l_en_q <= '0';
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r1e_addr_q <= (others => '0');
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r0e_byp_e_q <= '0';
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r0e_byp_l_q <= '0';
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r1e_byp_e_q <= '0';
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r1e_byp_l_q <= '0';
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else
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w0e_data_q <= w0e_data_func;
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w0l_data_q <= w0l_data_func;
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w0l_en_q <= w0l_en_func;
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w0l_addr_q <= w0l_addr_func;
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r1e_addr_q <= r1e_addr_func;
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r0e_byp_e_q <= r0e_byp_e;
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r0e_byp_l_q <= r0e_byp_l;
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r1e_byp_e_q <= r1e_byp_e;
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r1e_byp_l_q <= r1e_byp_l;
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end if;
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end if;
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end process;
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flatch: process (clk2x,reset_lo) begin
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if clk2x'event and clk2x = '1' then
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if (reset_lo = '0') then
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flipper_q <= '0';
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else
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flipper_q <= flipper_d;
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doutb0_q <= tconv(doutb0);
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end if;
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end if;
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end process;
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rlatch: process (correct_clk) begin
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if(rising_edge(correct_clk)) then
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reset_q <= reset_hi;
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sinit0_q <= reset_hi;
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sinit1_q <= reset_hi;
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end if;
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end process;
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addra(0) <= '0';
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addra(1 to 8) <= (tconv((w0e_addr_func and (0 to 7 => flipper_q)) or (w0l_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ;
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weaf <= (( w0e_en_func and flipper_q) or ( w0l_en_q and not flipper_q)) after 1 ns;
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dinfa <= (tconv((w0e_data_func and (0 to 77 => flipper_q)) or (w0l_data_q and (0 to 77 => not flipper_q)))) after 1 ns;
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dinfb <= (others => '0');
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addrb0(0) <= '0';
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addrb0(1 to 8) <= (tconv((r0e_addr_func and (0 to 7 => flipper_q)) or (r1e_addr_q and (0 to 7 => not flipper_q)))) after 1 ns ;
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r0_byp_sel <= r0e_byp_e & r0e_byp_l;
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with r0_byp_sel select
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r0e_data_out <= w0e_data_q when "10",
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w0l_data_q when "01",
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doutb0_q when others;
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r1_byp_sel <= r1e_byp_e & r1e_byp_l;
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with r1_byp_sel select
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r1e_data_out <= w0e_data_q when "10",
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w0l_data_q when "01",
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tconv(doutb0) when others;
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U0 : RAMB16_S36_S36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map
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(
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DOA => open,
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DOB => doutb0(0 to 31),
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DOPA => open,
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DOPB => open,
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ADDRA => addra,
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ADDRB => addrb0,
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CLKA => clk2x,
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CLKB => clk2x,
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DIA => dinfa(0 to 31),
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DIB => dinfb,
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DIPA => zeross,
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DIPB => zeross,
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ENA => tihi,
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ENB => tihi,
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SSRA => sinit0_q,
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SSRB => sinit0_q,
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WEA => weaf,
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WEB => tilo
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);
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U1 : RAMB16_S36_S36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map
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(
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DOA => open,
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DOB => doutb0(32 to 63),
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DOPA => open,
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DOPB => open,
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ADDRA => addra,
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ADDRB => addrb0,
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CLKA => clk2x,
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CLKB => clk2x,
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DIA => dinfa(32 to 63),
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DIB => dinfb,
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DIPA => zeross,
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DIPB => zeross,
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ENA => tihi,
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ENB => tihi,
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SSRA => sinit1_q,
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SSRB => sinit1_q,
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WEA => weaf,
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WEB => tilo
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);
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doutb0(64 to 77) <= doutb0_par(64 to 77);
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dinfa0_par(64 to 95) <= dinfa(64 to 77) & (78 to 95 => '0');
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U2 : RAMB16_S36_S36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map
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(
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DOA => open,
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DOB => doutb0_par(64 to 95),
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DOPA => open,
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DOPB => open,
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ADDRA => addra,
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ADDRB => addrb0,
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CLKA => clk2x,
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CLKB => clk2x,
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DIA => dinfa0_par(64 to 95),
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DIB => dinfb,
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DIPA => zeross,
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DIPB => zeross,
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ENA => tihi,
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ENB => tihi,
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SSRA => sinit1_q,
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SSRB => sinit1_q,
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WEA => weaf,
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WEB => tilo
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);
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r_scan_out <= '0';
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w_scan_out <= '0';
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time_scan_out <= '0';
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obs0_scan_out <= '0';
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obs1_scan_out <= '0';
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bo_pc_failout <= '0';
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bo_pc_diagloop <= '0';
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unused <= or_reduce( std_ulogic_vector(doutb0_par(78 to 95))
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& abist_en & abist_raw_dc_b & r0e_abist_comp_en & r1e_abist_comp_en
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& lbist_en & lcb_act_dis_dc & lcb_clkoff_dc_b & lcb_d_mode_dc
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& lcb_delay_lclkr_dc & lcb_fce_0 & lcb_mpw1_dc_b & lcb_mpw2_dc_b
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& lcb_scan_diag_dc & lcb_scan_dis_dc_b & lcb_sg_0 & lcb_time_sg_0
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& lcb_obs0_sg_0 & lcb_obs1_sg_0 & lcb_obs0_sl_thold_0 & lcb_obs1_sl_thold_0
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& lcb_abst_sl_thold_0 & lcb_time_sl_thold_0 & lcb_ary_nsl_thold_0
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& r_scan_in & w_scan_in & time_scan_in & obs0_scan_in & obs1_scan_in
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& r0e_act & r0e_en_func & r0e_en_abist & r0e_addr_abist & r0e_byp_r & r0e_sel_lbist
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& r1e_act & r1e_en_func & r1e_en_abist & r1e_addr_abist & r1e_byp_r & r1e_sel_lbist
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& w0e_act & w0e_en_abist & w0e_addr_abist & w0e_data_abist
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& w0l_act & w0l_en_abist & w0l_addr_abist & w0l_data_abist
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& lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
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& pc_bo_unload & pc_bo_load & pc_bo_shdata & pc_bo_select
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& tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
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& tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
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end generate;
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end architecture tri_144x78_2r2w;
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