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579 lines
22 KiB
VHDL
579 lines
22 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all ;
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library ibm; use ibm.std_ulogic_support.all ;
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use ibm.std_ulogic_function_support.all;
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library support; use support.power_logic_pkg.all;
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library tri; use tri.tri_latches_pkg.all;
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-- pragma translate_off
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-- pragma translate_on
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entity tri_32x35_8w_1r1w is
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generic (addressable_ports : positive := 32;
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addressbus_width : positive := 5;
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port_bitwidth : positive := 35;
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ways : positive := 8;
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expand_type : integer := 1);
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port (
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gnd : inout power_logic;
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vdd : inout power_logic;
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vcs : inout power_logic;
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nclk : in clk_logic;
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rd0_act : in std_ulogic;
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sg_0 : in std_ulogic;
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abst_slp_sl_thold_0 : in std_ulogic;
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ary_slp_nsl_thold_0 : in std_ulogic;
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time_sl_thold_0 : in std_ulogic;
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repr_sl_thold_0 : in std_ulogic;
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clkoff_dc_b : in std_ulogic;
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ccflush_dc : in std_ulogic;
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scan_dis_dc_b : in std_ulogic;
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scan_diag_dc : in std_ulogic;
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d_mode_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic_vector(0 to 4);
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mpw2_dc_b : in std_ulogic;
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delay_lclkr_dc : in std_ulogic_vector(0 to 4);
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wr_abst_act : in std_ulogic;
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rd0_abst_act : in std_ulogic;
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abist_di : in std_ulogic_vector(0 to 3);
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abist_bw_odd : in std_ulogic;
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abist_bw_even : in std_ulogic;
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abist_wr_adr : in std_ulogic_vector(0 to 4);
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abist_rd0_adr : in std_ulogic_vector(0 to 4);
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tc_lbist_ary_wrt_thru_dc : in std_ulogic;
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abist_ena_1 : in std_ulogic;
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abist_g8t_rd0_comp_ena : in std_ulogic;
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abist_raw_dc_b : in std_ulogic;
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obs0_abist_cmp : in std_ulogic_vector(0 to 3);
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abst_scan_in : in std_ulogic;
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time_scan_in : in std_ulogic;
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repr_scan_in : in std_ulogic;
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abst_scan_out : out std_ulogic;
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time_scan_out : out std_ulogic;
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repr_scan_out : out std_ulogic;
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lcb_bolt_sl_thold_0 : in std_ulogic;
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pc_bo_enable_2 : in std_ulogic;
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pc_bo_reset : in std_ulogic;
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pc_bo_unload : in std_ulogic;
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pc_bo_repair : in std_ulogic;
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pc_bo_shdata : in std_ulogic;
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pc_bo_select : in std_ulogic_vector(0 to 3);
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bo_pc_failout : out std_ulogic_vector(0 to 3);
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bo_pc_diagloop : out std_ulogic_vector(0 to 3);
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tri_lcb_mpw1_dc_b : in std_ulogic;
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tri_lcb_mpw2_dc_b : in std_ulogic;
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tri_lcb_delay_lclkr_dc : in std_ulogic;
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tri_lcb_clkoff_dc_b : in std_ulogic;
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tri_lcb_act_dis_dc : in std_ulogic;
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write_enable : in std_ulogic_vector (0 to ((port_bitwidth*ways-1)/(port_bitwidth*2)));
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way : in std_ulogic_vector (0 to (ways-1));
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addr_wr : in std_ulogic_vector (0 to (addressbus_width-1));
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data_in : in std_ulogic_vector (0 to (port_bitwidth-1));
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addr_rd_01 : in std_ulogic_vector (0 to (addressbus_width-1));
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addr_rd_23 : in std_ulogic_vector (0 to (addressbus_width-1));
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addr_rd_45 : in std_ulogic_vector (0 to (addressbus_width-1));
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addr_rd_67 : in std_ulogic_vector (0 to (addressbus_width-1));
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data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end entity tri_32x35_8w_1r1w;
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architecture tri_32x35_8w_1r1w of tri_32x35_8w_1r1w is
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constant wga_base_width : integer := 70;
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constant wga_base_addr : integer := 5;
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constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
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constant ramb_base_width : integer := 36;
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constant ramb_base_addr : integer := 9;
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constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;
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begin
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-- synopsys translate_off
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um: if expand_type = 0 generate
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signal tiup : std_ulogic;
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signal tidn : std_ulogic;
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signal addr_rd_l2 : std_ulogic_vector (0 TO addressbus_width-1);
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signal addr_wr_l2 : std_ulogic_vector (0 TO addressbus_width-1);
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signal way_l2 : std_ulogic_vector (0 TO way'right);
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signal write_enable_d : std_ulogic_vector(0 to wga_width_mult-1);
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signal write_enable_l2 : std_ulogic_vector(0 to wga_width_mult-1);
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signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth-1);
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signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
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signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
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signal act : std_ulogic;
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begin
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tiup <= '1';
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tidn <= '0';
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act <= or_reduce(write_enable) or rd0_act;
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addr_rd_latch: tri_rlmreg_p
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generic map (width => addr_rd_01'length, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => act,
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scin => (others => '0'),
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scout => open,
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din => addr_rd_01,
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dout => addr_rd_l2 );
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addr_wr_latch: tri_rlmreg_p
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generic map (width => addr_wr'length, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => act,
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scin => (others => '0'),
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scout => open,
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din => addr_wr,
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dout => addr_wr_l2 );
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way_latch: tri_rlmreg_p
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generic map (width => way'length, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => act,
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scin => (others => '0'),
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scout => open,
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din => way,
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dout => way_l2 );
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write_enable_latch: tri_rlmreg_p
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generic map (width => wga_width_mult, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => act,
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scin => (others => '0'),
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scout => open,
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din => write_enable_d,
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dout => write_enable_l2 );
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data_in_latch: tri_rlmreg_p
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generic map (width => port_bitwidth, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => act,
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scin => (others => '0'),
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scout => open,
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din => data_in,
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dout => data_in_l2 );
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array_latch: tri_rlmreg_p
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generic map (width => addressable_ports*port_bitwidth*ways, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => tiup,
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scin => (others => '0'),
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scout => open,
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din => array_d,
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dout => array_l2 );
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write_enable_d <= write_enable;
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ww: for w in 0 to ways-1 generate
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begin
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wy: for y in 0 to addressable_ports-1 generate
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begin
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wx: for x in 0 to port_bitwidth-1 generate
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begin
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array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
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data_in_l2(x) when (( or_reduce(write_enable_l2) and addr_wr_l2 = tconv(y, addressbus_width) and
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way_l2(w)) = '1')
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else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
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end generate wx;
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end generate wy;
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end generate ww;
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data_out <= array_l2( tconv(addr_rd_l2)*port_bitwidth*ways to tconv(addr_rd_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
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abst_scan_out <= tidn;
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time_scan_out <= tidn;
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repr_scan_out <= tidn;
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bo_pc_failout <= "0000";
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bo_pc_diagloop <= "0000";
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end generate um;
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-- synopsys translate_on
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a: if expand_type = 1 generate
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component RAMB16_S36_S36
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-- pragma translate_off
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generic(
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SIM_COLLISION_CHECK : string := "none");
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-- pragma translate_on
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port(
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DOA : out std_logic_vector(31 downto 0);
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DOB : out std_logic_vector(31 downto 0);
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DOPA : out std_logic_vector(3 downto 0);
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DOPB : out std_logic_vector(3 downto 0);
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ADDRA : in std_logic_vector(8 downto 0);
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ADDRB : in std_logic_vector(8 downto 0);
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector(31 downto 0);
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DIB : in std_logic_vector(31 downto 0);
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DIPA : in std_logic_vector(3 downto 0);
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DIPB : in std_logic_vector(3 downto 0);
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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SSRA : in std_ulogic;
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SSRB : in std_ulogic;
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WEA : in std_ulogic;
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WEB : in std_ulogic);
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end component;
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-- pragma translate_off
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-- pragma translate_on
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signal array_wr_data : std_logic_vector(0 to port_bitwidth - 1);
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signal ramb_data_in : std_logic_vector(0 to 35);
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signal ramb_data_outA : std_logic_vector(0 to 35);
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signal ramb_data_outB : std_logic_vector(0 to 35);
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signal ramb_data_outC : std_logic_vector(0 to 35);
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signal ramb_data_outD : std_logic_vector(0 to 35);
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signal ramb_data_outE : std_logic_vector(0 to 35);
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signal ramb_data_outF : std_logic_vector(0 to 35);
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signal ramb_data_outG : std_logic_vector(0 to 35);
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signal ramb_data_outH : std_logic_vector(0 to 35);
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signal ramb_addr_wr : std_logic_vector(0 to ramb_base_addr - 1);
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signal ramb_addr_rd : std_logic_vector(0 to ramb_base_addr - 1);
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signal data_outA : std_ulogic_vector(0 to 35);
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signal data_outB : std_ulogic_vector(0 to 35);
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signal data_outC : std_ulogic_vector(0 to 35);
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signal data_outD : std_ulogic_vector(0 to 35);
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signal data_outE : std_ulogic_vector(0 to 35);
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signal data_outF : std_ulogic_vector(0 to 35);
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signal data_outG : std_ulogic_vector(0 to 35);
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signal data_outH : std_ulogic_vector(0 to 35);
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signal rd_addr : std_ulogic_vector(0 to ramb_base_addr - 1);
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signal wr_addr : std_ulogic_vector(0 to ramb_base_addr - 1);
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signal write_enable_wA : std_ulogic;
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signal write_enable_wB : std_ulogic;
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signal write_enable_wC : std_ulogic;
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signal write_enable_wD : std_ulogic;
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signal write_enable_wE : std_ulogic;
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signal write_enable_wF : std_ulogic;
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signal write_enable_wG : std_ulogic;
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signal write_enable_wH : std_ulogic;
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signal tidn : std_logic_vector(0 to 35);
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signal act : std_ulogic;
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signal wen : std_ulogic;
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signal unused : std_ulogic;
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-- synopsys translate_off
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-- synopsys translate_on
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begin
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tidn <= (others=>'0');
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wen <= or_reduce(write_enable);
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act <= rd0_act or wen;
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array_wr_data <= tconv(data_in);
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addr_calc : for t in 0 to 35 generate begin
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R0 : if(t < 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= '0'; end generate;
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R1 : if(t >= 35 - (port_bitwidth-1)) generate begin ramb_data_in(t) <= array_wr_data(t-(35-(port_bitwidth-1))); end generate;
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end generate addr_calc;
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write_enable_wA <= wen and way(0);
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write_enable_wB <= wen and way(1);
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write_enable_wC <= wen and way(2);
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write_enable_wD <= wen and way(3);
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write_enable_wE <= wen and way(4);
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write_enable_wF <= wen and way(5);
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write_enable_wG <= wen and way(6);
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write_enable_wH <= wen and way(7);
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rambAddrCalc : for t in 0 to ramb_base_addr-1 generate begin
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R0 : if(t < ramb_base_addr-addressbus_width) generate begin
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rd_addr(t) <= '0';
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wr_addr(t) <= '0';
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end generate;
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R1 : if(t >= ramb_base_addr-addressbus_width) generate begin
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rd_addr(t) <= addr_rd_01(t-(ramb_base_addr-addressbus_width));
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wr_addr(t) <= addr_wr(t-(ramb_base_addr-addressbus_width));
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end generate;
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end generate rambAddrCalc;
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ramb_addr_wr <= tconv(wr_addr);
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ramb_addr_rd <= tconv(rd_addr);
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data_outA <= tconv(ramb_data_outA);
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data_outB <= tconv(ramb_data_outB);
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data_outC <= tconv(ramb_data_outC);
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data_outD <= tconv(ramb_data_outD);
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data_outE <= tconv(ramb_data_outE);
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data_outF <= tconv(ramb_data_outF);
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data_outG <= tconv(ramb_data_outG);
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data_outH <= tconv(ramb_data_outH);
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data_out <= data_outA((35-(port_bitwidth-1)) to 35) & data_outB((35-(port_bitwidth-1)) to 35) &
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data_outC((35-(port_bitwidth-1)) to 35) & data_outD((35-(port_bitwidth-1)) to 35) &
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data_outE((35-(port_bitwidth-1)) to 35) & data_outF((35-(port_bitwidth-1)) to 35) &
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data_outG((35-(port_bitwidth-1)) to 35) & data_outH((35-(port_bitwidth-1)) to 35);
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arr0_A: RAMB16_S36_S36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map(
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DOA => ramb_data_outA(0 to 31),
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DOB => open,
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DOPA => ramb_data_outA(32 to 35),
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DOPB => open,
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ADDRA => ramb_addr_rd,
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ADDRB => ramb_addr_wr,
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CLKA => nclk.clk,
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CLKB => nclk.clk,
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DIA => tidn(0 to 31),
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DIB => ramb_data_in(0 to 31),
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DIPA => tidn(32 to 35),
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DIPB => ramb_data_in(32 to 35),
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ENA => act,
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ENB => act,
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SSRA => nclk.sreset,
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SSRB => nclk.sreset,
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WEA => tidn(0),
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WEB => write_enable_wA
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);
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arr1_B: RAMB16_S36_S36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map(
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DOA => ramb_data_outB(0 to 31),
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DOB => open,
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DOPA => ramb_data_outB(32 to 35),
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DOPB => open,
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ADDRA => ramb_addr_rd,
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ADDRB => ramb_addr_wr,
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CLKA => nclk.clk,
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CLKB => nclk.clk,
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DIA => tidn(0 to 31),
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DIB => ramb_data_in(0 to 31),
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DIPA => tidn(32 to 35),
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DIPB => ramb_data_in(32 to 35),
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ENA => act,
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ENB => act,
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SSRA => nclk.sreset,
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SSRB => nclk.sreset,
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WEA => tidn(0),
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WEB => write_enable_wB
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);
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arr2_C: RAMB16_S36_S36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map(
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DOA => ramb_data_outC(0 to 31),
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DOB => open,
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DOPA => ramb_data_outC(32 to 35),
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DOPB => open,
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ADDRA => ramb_addr_rd,
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ADDRB => ramb_addr_wr,
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CLKA => nclk.clk,
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CLKB => nclk.clk,
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DIA => tidn(0 to 31),
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DIB => ramb_data_in(0 to 31),
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DIPA => tidn(32 to 35),
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DIPB => ramb_data_in(32 to 35),
|
|
ENA => act,
|
|
ENB => act,
|
|
SSRA => nclk.sreset,
|
|
SSRB => nclk.sreset,
|
|
WEA => tidn(0),
|
|
WEB => write_enable_wC
|
|
);
|
|
|
|
arr3_D: RAMB16_S36_S36
|
|
-- pragma translate_off
|
|
generic map(
|
|
sim_collision_check => "none")
|
|
-- pragma translate_on
|
|
port map(
|
|
DOA => ramb_data_outD(0 to 31),
|
|
DOB => open,
|
|
DOPA => ramb_data_outD(32 to 35),
|
|
DOPB => open,
|
|
ADDRA => ramb_addr_rd,
|
|
ADDRB => ramb_addr_wr,
|
|
CLKA => nclk.clk,
|
|
CLKB => nclk.clk,
|
|
DIA => tidn(0 to 31),
|
|
DIB => ramb_data_in(0 to 31),
|
|
DIPA => tidn(32 to 35),
|
|
DIPB => ramb_data_in(32 to 35),
|
|
ENA => act,
|
|
ENB => act,
|
|
SSRA => nclk.sreset,
|
|
SSRB => nclk.sreset,
|
|
WEA => tidn(0),
|
|
WEB => write_enable_wD
|
|
);
|
|
|
|
arr4_E: RAMB16_S36_S36
|
|
-- pragma translate_off
|
|
generic map(
|
|
sim_collision_check => "none")
|
|
-- pragma translate_on
|
|
port map(
|
|
DOA => ramb_data_outE(0 to 31),
|
|
DOB => open,
|
|
DOPA => ramb_data_outE(32 to 35),
|
|
DOPB => open,
|
|
ADDRA => ramb_addr_rd,
|
|
ADDRB => ramb_addr_wr,
|
|
CLKA => nclk.clk,
|
|
CLKB => nclk.clk,
|
|
DIA => tidn(0 to 31),
|
|
DIB => ramb_data_in(0 to 31),
|
|
DIPA => tidn(32 to 35),
|
|
DIPB => ramb_data_in(32 to 35),
|
|
ENA => act,
|
|
ENB => act,
|
|
SSRA => nclk.sreset,
|
|
SSRB => nclk.sreset,
|
|
WEA => tidn(0),
|
|
WEB => write_enable_wE
|
|
);
|
|
|
|
arr5_F: RAMB16_S36_S36
|
|
-- pragma translate_off
|
|
generic map(
|
|
sim_collision_check => "none")
|
|
-- pragma translate_on
|
|
port map(
|
|
DOA => ramb_data_outF(0 to 31),
|
|
DOB => open,
|
|
DOPA => ramb_data_outF(32 to 35),
|
|
DOPB => open,
|
|
ADDRA => ramb_addr_rd,
|
|
ADDRB => ramb_addr_wr,
|
|
CLKA => nclk.clk,
|
|
CLKB => nclk.clk,
|
|
DIA => tidn(0 to 31),
|
|
DIB => ramb_data_in(0 to 31),
|
|
DIPA => tidn(32 to 35),
|
|
DIPB => ramb_data_in(32 to 35),
|
|
ENA => act,
|
|
ENB => act,
|
|
SSRA => nclk.sreset,
|
|
SSRB => nclk.sreset,
|
|
WEA => tidn(0),
|
|
WEB => write_enable_wF
|
|
);
|
|
|
|
arr6_G: RAMB16_S36_S36
|
|
-- pragma translate_off
|
|
generic map(
|
|
sim_collision_check => "none")
|
|
-- pragma translate_on
|
|
port map(
|
|
DOA => ramb_data_outG(0 to 31),
|
|
DOB => open,
|
|
DOPA => ramb_data_outG(32 to 35),
|
|
DOPB => open,
|
|
ADDRA => ramb_addr_rd,
|
|
ADDRB => ramb_addr_wr,
|
|
CLKA => nclk.clk,
|
|
CLKB => nclk.clk,
|
|
DIA => tidn(0 to 31),
|
|
DIB => ramb_data_in(0 to 31),
|
|
DIPA => tidn(32 to 35),
|
|
DIPB => ramb_data_in(32 to 35),
|
|
ENA => act,
|
|
ENB => act,
|
|
SSRA => nclk.sreset,
|
|
SSRB => nclk.sreset,
|
|
WEA => tidn(0),
|
|
WEB => write_enable_wG
|
|
);
|
|
|
|
arr7_H: RAMB16_S36_S36
|
|
-- pragma translate_off
|
|
generic map(
|
|
sim_collision_check => "none")
|
|
-- pragma translate_on
|
|
port map(
|
|
DOA => ramb_data_outH(0 to 31),
|
|
DOB => open,
|
|
DOPA => ramb_data_outH(32 to 35),
|
|
DOPB => open,
|
|
ADDRA => ramb_addr_rd,
|
|
ADDRB => ramb_addr_wr,
|
|
CLKA => nclk.clk,
|
|
CLKB => nclk.clk,
|
|
DIA => tidn(0 to 31),
|
|
DIB => ramb_data_in(0 to 31),
|
|
DIPA => tidn(32 to 35),
|
|
DIPB => ramb_data_in(32 to 35),
|
|
ENA => act,
|
|
ENB => act,
|
|
SSRA => nclk.sreset,
|
|
SSRB => nclk.sreset,
|
|
WEA => tidn(0),
|
|
WEB => write_enable_wH
|
|
);
|
|
|
|
abst_scan_out <= tidn(0);
|
|
time_scan_out <= tidn(0);
|
|
repr_scan_out <= tidn(0);
|
|
|
|
bo_pc_failout <= "0000";
|
|
bo_pc_diagloop <= "0000";
|
|
|
|
unused <= or_reduce( data_outA(0) & data_outB(0) & data_outC(0) & data_outD(0)
|
|
& data_outE(0) & data_outF(0) & data_outG(0) & data_outH(0)
|
|
& sg_0 & abst_slp_sl_thold_0 & ary_slp_nsl_thold_0
|
|
& time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc
|
|
& scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b
|
|
& delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di
|
|
& abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
|
|
& tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
|
|
& abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in
|
|
& repr_scan_in & addr_rd_23 & addr_rd_45 & addr_rd_67
|
|
& lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
|
|
& pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
|
|
& tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
|
|
& tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
|
|
end generate a;
|
|
|
|
end tri_32x35_8w_1r1w;
|
|
|