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358 lines
15 KiB
VHDL
358 lines
15 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all ;
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library ibm; use ibm.std_ulogic_support.all ;
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use ibm.std_ulogic_function_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri; use tri.tri_latches_pkg.all;
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-- pragma translate_off
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-- pragma translate_on
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entity tri_64x36_4w_1r1w is
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generic (addressable_ports : positive := 64;
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addressbus_width : positive := 6;
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port_bitwidth : positive := 36;
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ways : positive := 4;
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expand_type : integer := 1);
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port (
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gnd : inout power_logic;
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vdd : inout power_logic;
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vcs : inout power_logic;
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nclk : in clk_logic;
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rd_act : in std_ulogic;
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wr_act : in std_ulogic;
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sg_0 : in std_ulogic;
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abst_sl_thold_0 : in std_ulogic;
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ary_nsl_thold_0 : in std_ulogic;
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time_sl_thold_0 : in std_ulogic;
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repr_sl_thold_0 : in std_ulogic;
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clkoff_dc_b : in std_ulogic;
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ccflush_dc : in std_ulogic;
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scan_dis_dc_b : in std_ulogic;
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scan_diag_dc : in std_ulogic;
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d_mode_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic_vector(0 to 4);
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mpw2_dc_b : in std_ulogic;
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delay_lclkr_dc : in std_ulogic_vector(0 to 4);
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wr_abst_act : in std_ulogic;
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rd0_abst_act : in std_ulogic;
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abist_di : in std_ulogic_vector(0 to 3);
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abist_bw_odd : in std_ulogic;
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abist_bw_even : in std_ulogic;
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abist_wr_adr : in std_ulogic_vector(0 to 5);
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abist_rd0_adr : in std_ulogic_vector(0 to 5);
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tc_lbist_ary_wrt_thru_dc : in std_ulogic;
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abist_ena_1 : in std_ulogic;
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abist_g8t_rd0_comp_ena : in std_ulogic;
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abist_raw_dc_b : in std_ulogic;
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obs0_abist_cmp : in std_ulogic_vector(0 to 3);
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abst_scan_in : in std_ulogic_vector(0 to 1);
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time_scan_in : in std_ulogic;
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repr_scan_in : in std_ulogic;
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abst_scan_out : out std_ulogic_vector(0 to 1);
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time_scan_out : out std_ulogic;
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repr_scan_out : out std_ulogic;
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lcb_bolt_sl_thold_0 : in std_ulogic;
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pc_bo_enable_2 : in std_ulogic;
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pc_bo_reset : in std_ulogic;
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pc_bo_unload : in std_ulogic;
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pc_bo_repair : in std_ulogic;
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pc_bo_shdata : in std_ulogic;
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pc_bo_select : in std_ulogic_vector(0 to 1);
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bo_pc_failout : out std_ulogic_vector(0 to 1);
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bo_pc_diagloop : out std_ulogic_vector(0 to 1);
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tri_lcb_mpw1_dc_b : in std_ulogic;
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tri_lcb_mpw2_dc_b : in std_ulogic;
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tri_lcb_delay_lclkr_dc : in std_ulogic;
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tri_lcb_clkoff_dc_b : in std_ulogic;
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tri_lcb_act_dis_dc : in std_ulogic;
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wr_way : in std_ulogic_vector (0 to (ways-1));
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wr_addr : in std_ulogic_vector (0 to (addressbus_width-1));
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data_in : in std_ulogic_vector (0 to (port_bitwidth*ways-1));
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rd_addr : in std_ulogic_vector(0 to (addressbus_width-1));
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data_out : out std_ulogic_vector(0 to (port_bitwidth*ways-1))
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end entity tri_64x36_4w_1r1w;
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architecture tri_64x36_4w_1r1w of tri_64x36_4w_1r1w is
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constant wga_base_width : integer := 72;
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constant wga_width_mult : integer := (port_bitwidth*ways-1)/wga_base_width + 1;
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constant ramb_base_width : integer := 36;
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constant ramb_base_addr : integer := 9;
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constant ramb_width_mult : integer := (port_bitwidth-1)/ramb_base_width + 1;
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type RAMB_DATA_ARRAY is array (natural range <>) of std_logic_vector(0 to (ramb_base_width*ramb_width_mult - 1));
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begin
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-- synopsys translate_off
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um: if expand_type = 0 generate
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signal tiup : std_ulogic;
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signal tidn : std_ulogic;
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signal wr_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1);
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signal rd_addr_l2 : std_ulogic_vector (0 TO addressbus_width-1);
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signal way_l2 : std_ulogic_vector (0 TO wr_way'right);
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signal write_enable_l2 : std_ulogic;
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signal data_in_l2 : std_ulogic_vector(0 to port_bitwidth*ways-1);
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signal array_d : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
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signal array_l2 : std_ulogic_vector(0 to addressable_ports*port_bitwidth*ways-1);
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begin
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tiup <= '1';
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tidn <= '0';
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wr_addr_latch: tri_rlmreg_p
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generic map (width => wr_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => wr_act,
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scin => (others => '0'),
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scout => open,
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din => wr_addr,
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dout => wr_addr_l2 );
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rd_addr_latch: tri_rlmreg_p
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generic map (width => rd_addr'length, init => 0, needs_sreset => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => rd_act,
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scin => (others => '0'),
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scout => open,
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din => rd_addr,
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dout => rd_addr_l2 );
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way_latch: tri_rlmreg_p
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generic map (width => wr_way'length, init => 0, needs_sreset => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => wr_act,
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scin => (others => '0'),
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scout => open,
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din => wr_way,
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dout => way_l2 );
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write_enable_latch: tri_rlmlatch_p
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generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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scin => tidn,
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scout => open,
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din => wr_act,
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dout => write_enable_l2 );
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data_in_latch: tri_rlmreg_p
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generic map (width => port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => wr_act,
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scin => (others => '0'),
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scout => open,
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din => data_in,
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dout => data_in_l2 );
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array_latch: tri_rlmreg_p
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generic map (width => addressable_ports*port_bitwidth*ways, init => 0, needs_sreset => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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scin => (others => '0'),
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scout => open,
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din => array_d,
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dout => array_l2 );
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ww: for w in 0 to ways-1 generate
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begin
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wy: for y in 0 to addressable_ports-1 generate
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begin
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wx: for x in 0 to port_bitwidth-1 generate
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begin
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array_d(y*port_bitwidth*ways+w*port_bitwidth+x) <=
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data_in_l2(w*port_bitwidth+x) when (( write_enable_l2 and wr_addr_l2 = tconv(y, addressbus_width) and
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way_l2(w)) = '1')
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else array_l2(y*port_bitwidth*ways+w*port_bitwidth+x);
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end generate wx;
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end generate wy;
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end generate ww;
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data_out <= array_l2( tconv(rd_addr_l2)*port_bitwidth*ways to tconv(rd_addr_l2)*port_bitwidth*ways+port_bitwidth*ways-1 );
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abst_scan_out <= tidn & tidn;
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time_scan_out <= tidn;
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repr_scan_out <= tidn;
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bo_pc_failout <= tidn & tidn;
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bo_pc_diagloop <= tidn & tidn;
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end generate um;
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-- synopsys translate_on
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a: if expand_type = 1 generate
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component RAMB16_S36_S36
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-- pragma translate_off
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generic
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(
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SIM_COLLISION_CHECK : string := "none");
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-- pragma translate_on
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port
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(
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DOA : out std_logic_vector(31 downto 0);
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DOB : out std_logic_vector(31 downto 0);
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DOPA : out std_logic_vector(3 downto 0);
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DOPB : out std_logic_vector(3 downto 0);
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ADDRA : in std_logic_vector(8 downto 0);
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ADDRB : in std_logic_vector(8 downto 0);
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector(31 downto 0);
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DIB : in std_logic_vector(31 downto 0);
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DIPA : in std_logic_vector(3 downto 0);
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DIPB : in std_logic_vector(3 downto 0);
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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SSRA : in std_ulogic;
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SSRB : in std_ulogic;
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WEA : in std_ulogic;
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WEB : in std_ulogic
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);
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end component;
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-- pragma translate_off
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-- pragma translate_on
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signal ramb_data_in : RAMB_DATA_ARRAY(wr_way'range);
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signal ramb_data_out : RAMB_DATA_ARRAY(wr_way'range);
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signal ramb_rd_addr : std_logic_vector(0 to ramb_base_addr - 1);
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signal ramb_wr_addr : std_logic_vector(0 to ramb_base_addr - 1);
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signal tidn : std_ulogic;
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signal unused : std_ulogic;
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-- synopsys translate_off
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-- synopsys translate_on
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begin
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tidn <= '0';
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add0: if (addressbus_width < ramb_base_addr) generate
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begin
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ramb_rd_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
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ramb_rd_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( rd_addr );
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ramb_wr_addr(0 to (ramb_base_addr-addressbus_width-1)) <= (others => '0');
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ramb_wr_addr(ramb_base_addr-addressbus_width to ramb_base_addr-1) <= tconv( wr_addr );
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end generate;
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add1: if (addressbus_width >= ramb_base_addr) generate
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begin
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ramb_rd_addr <= tconv( rd_addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
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ramb_wr_addr <= tconv( wr_addr(addressbus_width-ramb_base_addr to addressbus_width-1) );
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end generate;
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dw: for w in wr_way'range generate begin
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din: for i in 0 to (ramb_base_width*ramb_width_mult - 1) generate
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begin
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R0: if(i < port_bitwidth) generate begin ramb_data_in(w)(i) <= data_in(w*port_bitwidth+i); end generate;
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R1: if(i >= port_bitwidth) generate begin ramb_data_in(w)(i) <= '0'; end generate;
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end generate din;
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end generate dw;
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aw: for w in wr_way'range generate begin
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ax: for x in 0 to (ramb_width_mult - 1) generate begin
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arr: RAMB16_S36_S36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map(
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DOA => ramb_data_out(w)(x*ramb_base_width to x*ramb_base_width+31),
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DOB => open,
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DOPA => ramb_data_out(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
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DOPB => open,
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ADDRA => ramb_rd_addr,
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ADDRB => ramb_wr_addr,
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CLKA => nclk.clk,
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CLKB => nclk.clk,
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DIA => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31),
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DIB => ramb_data_in(w)(x*ramb_base_width to x*ramb_base_width+31),
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DIPA => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
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DIPB => ramb_data_in(w)(x*ramb_base_width+32 to x*ramb_base_width+35),
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ENA => rd_act,
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ENB => wr_act,
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SSRA => nclk.sreset,
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SSRB => nclk.sreset,
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WEA => tidn,
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WEB => wr_way(w)
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);
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end generate ax;
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data_out(w*port_bitwidth to ((w+1)*port_bitwidth)-1 ) <= tconv( ramb_data_out(w)(0 to port_bitwidth-1) );
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end generate aw;
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abst_scan_out <= tidn & tidn;
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time_scan_out <= tidn;
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repr_scan_out <= tidn;
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bo_pc_failout <= tidn & tidn;
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bo_pc_diagloop <= tidn & tidn;
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unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0
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& time_sl_thold_0 & repr_sl_thold_0 & clkoff_dc_b & ccflush_dc
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& scan_dis_dc_b & scan_diag_dc & d_mode_dc & mpw1_dc_b & mpw2_dc_b
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& delay_lclkr_dc & wr_abst_act & rd0_abst_act & abist_di
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& abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
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& tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
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& abist_raw_dc_b & obs0_abist_cmp & abst_scan_in & time_scan_in
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& repr_scan_in & lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
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& pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
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& tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
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& tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
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end generate a;
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end tri_64x36_4w_1r1w;
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