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286 lines
10 KiB
VHDL
286 lines
10 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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-- pragma translate_off
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-- pragma translate_on
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entity tri_64x72_1r1w is
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generic(
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expand_type : integer := 1;
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regsize : integer := 64);
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port (
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vdd : INOUT power_logic;
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vcs : INOUT power_logic;
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gnd : INOUT power_logic;
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nclk : in clk_logic;
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sg_0 : in std_ulogic;
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abst_sl_thold_0 : in std_ulogic;
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ary_nsl_thold_0 : in std_ulogic;
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time_sl_thold_0 : in std_ulogic;
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repr_sl_thold_0 : in std_ulogic;
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rd0_act : in std_ulogic;
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rd0_adr : in std_ulogic_vector(0 to 5);
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do0 : out std_ulogic_vector(64-regsize to 72-(64/regsize));
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wr_act : in std_ulogic;
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wr_adr : in std_ulogic_vector(0 to 5);
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di : in std_ulogic_vector(64-regsize to 72-(64/regsize));
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abst_scan_in : in std_ulogic;
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abst_scan_out : out std_ulogic;
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time_scan_in : in std_ulogic;
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time_scan_out : out std_ulogic;
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repr_scan_in : in std_ulogic;
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repr_scan_out : out std_ulogic;
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scan_dis_dc_b : in std_ulogic;
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scan_diag_dc : in std_ulogic;
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ccflush_dc : in std_ulogic;
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clkoff_dc_b : in std_ulogic;
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d_mode_dc : in std_ulogic;
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mpw1_dc_b : in std_ulogic_vector(0 to 4);
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mpw2_dc_b : in std_ulogic;
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delay_lclkr_dc : in std_ulogic_vector(0 to 4);
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lcb_bolt_sl_thold_0 : in std_ulogic;
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pc_bo_enable_2 : in std_ulogic;
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pc_bo_reset : in std_ulogic;
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pc_bo_unload : in std_ulogic;
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pc_bo_repair : in std_ulogic;
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pc_bo_shdata : in std_ulogic;
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pc_bo_select : in std_ulogic;
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bo_pc_failout : out std_ulogic;
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bo_pc_diagloop : out std_ulogic;
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tri_lcb_mpw1_dc_b : in std_ulogic;
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tri_lcb_mpw2_dc_b : in std_ulogic;
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tri_lcb_delay_lclkr_dc : in std_ulogic;
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tri_lcb_clkoff_dc_b : in std_ulogic;
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tri_lcb_act_dis_dc : in std_ulogic;
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abist_di : in std_ulogic_vector(0 to 3);
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abist_bw_odd : in std_ulogic;
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abist_bw_even : in std_ulogic;
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abist_wr_adr : in std_ulogic_vector(0 to 5);
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wr_abst_act : in std_ulogic;
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abist_rd0_adr : in std_ulogic_vector(0 to 5);
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rd0_abst_act : in std_ulogic;
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tc_lbist_ary_wrt_thru_dc : in std_ulogic;
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abist_ena_1 : in std_ulogic;
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abist_g8t_rd0_comp_ena : in std_ulogic;
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abist_raw_dc_b : in std_ulogic;
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obs0_abist_cmp : in std_ulogic_vector(0 to 3)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end entity tri_64x72_1r1w;
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architecture tri_64x72_1r1w of tri_64x72_1r1w is
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begin
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a : if expand_type = 1 generate
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component RAMB16_S36_S36
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-- pragma translate_off
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generic(
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SIM_COLLISION_CHECK : string := "none");
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-- pragma translate_on
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port(
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DOA : out std_logic_vector(31 downto 0);
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DOB : out std_logic_vector(31 downto 0);
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DOPA : out std_logic_vector(3 downto 0);
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DOPB : out std_logic_vector(3 downto 0);
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ADDRA : in std_logic_vector(8 downto 0);
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ADDRB : in std_logic_vector(8 downto 0);
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector(31 downto 0);
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DIB : in std_logic_vector(31 downto 0);
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DIPA : in std_logic_vector(3 downto 0);
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DIPB : in std_logic_vector(3 downto 0);
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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SSRA : in std_ulogic;
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SSRB : in std_ulogic;
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WEA : in std_ulogic;
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WEB : in std_ulogic);
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end component;
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-- pragma translate_off
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-- pragma translate_on
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signal clk, clk2x : std_ulogic;
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signal addra, addrb : std_ulogic_vector(0 to 8);
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signal wea, web : std_ulogic;
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signal bdo : std_logic_vector(0 to 71);
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signal bdi : std_ulogic_vector(0 to 71);
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signal sreset : std_ulogic;
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signal tidn : std_ulogic_vector(0 to 71);
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signal reset_q : std_ulogic;
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signal gate_fq, gate_d : std_ulogic;
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signal bdo_d, bdo_fq : std_ulogic_vector(64-regsize to 72-(64/regsize));
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signal toggle_d : std_ulogic;
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signal toggle_q : std_ulogic;
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signal toggle2x_d : std_ulogic;
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signal toggle2x_q : std_ulogic;
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signal unused : std_ulogic;
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-- synopsys translate_off
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-- synopsys translate_on
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begin
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tidn <= (others=>'0');
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clk <= nclk.clk;
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clk2x <= nclk.clk2x;
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sreset<= nclk.sreset;
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rlatch: process (clk) begin
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if(rising_edge(clk)) then
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reset_q <= sreset after 10 ps;
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end if;
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end process;
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tlatch: process (nclk.clk,reset_q)
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begin
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if(rising_edge(nclk.clk)) then
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if (reset_q = '1') then
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toggle_q <= '1';
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else
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toggle_q <= toggle_d;
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end if;
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end if;
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end process;
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flatch: process (nclk.clk2x)
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begin
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if(rising_edge(nclk.clk2x)) then
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toggle2x_q <= toggle2x_d;
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gate_fq <= gate_d;
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bdo_fq <= bdo_d;
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end if;
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end process;
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toggle_d <= not toggle_q;
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toggle2x_d <= toggle_q;
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gate_d <= not(toggle_q xor toggle2x_q);
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in32 : if regsize = 32 generate
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bdi <= tidn(0 to 31) & di(32 to 63) & di(64 to 70) & tidn(71);
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end generate;
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in64 : if regsize = 64 generate
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bdi <= di(0 to 71);
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end generate;
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bdo_d <= std_ulogic_vector(bdo(64-regsize to 72-(64/regsize)));
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do0 <= bdo_fq;
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wea <= (wr_act and gate_fq) after 10 ps;
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web <= (wr_act and gate_fq) after 10 ps;
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with gate_fq select
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addra <= ("00" & wr_adr & '0') after 10 ps when '1',
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("00" & rd0_adr & '0') after 10 ps when others;
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with gate_fq select
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addrb <= ("00" & wr_adr & '1') after 10 ps when '1',
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("00" & rd0_adr & '1') after 10 ps when others;
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bram0a : ramb16_s36_s36
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-- pragma translate_off
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generic map(
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sim_collision_check => "none")
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-- pragma translate_on
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port map(
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clka => clk2x,
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clkb => clk2x,
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ssra => sreset,
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ssrb => sreset,
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addra => std_logic_vector(addra),
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addrb => std_logic_vector(addrb),
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dia => std_logic_vector(bdi(00 to 31)),
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dib => std_logic_vector(bdi(32 to 63)),
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dipa => std_logic_vector(bdi(64 to 67)),
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dipb => std_logic_vector(bdi(68 to 71)),
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doa => bdo(00 to 31),
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dob => bdo(32 to 63),
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dopa => bdo(64 to 67),
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dopb => bdo(68 to 71),
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ena => '1',
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enb => '1',
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wea => wea,
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web => web
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);
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abst_scan_out <= abst_scan_in;
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time_scan_out <= time_scan_in;
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repr_scan_out <= repr_scan_in;
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bo_pc_failout <= '0';
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bo_pc_diagloop <= '0';
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unused <= or_reduce( sg_0 & abst_sl_thold_0 & ary_nsl_thold_0 & time_sl_thold_0 & repr_sl_thold_0
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& scan_dis_dc_b & scan_diag_dc & ccflush_dc
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& clkoff_dc_b & d_mode_dc & mpw1_dc_b & mpw2_dc_b
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& delay_lclkr_dc & abist_di
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& abist_bw_odd & abist_bw_even & abist_wr_adr & abist_rd0_adr
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& wr_abst_act & rd0_abst_act
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& tc_lbist_ary_wrt_thru_dc & abist_ena_1 & abist_g8t_rd0_comp_ena
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& abist_raw_dc_b & obs0_abist_cmp & rd0_act & tidn
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& lcb_bolt_sl_thold_0 & pc_bo_enable_2 & pc_bo_reset
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& pc_bo_unload & pc_bo_repair & pc_bo_shdata & pc_bo_select
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& tri_lcb_mpw1_dc_b & tri_lcb_mpw2_dc_b & tri_lcb_delay_lclkr_dc
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& tri_lcb_clkoff_dc_b & tri_lcb_act_dis_dc );
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end generate;
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end architecture tri_64x72_1r1w;
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