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502 lines
21 KiB
VHDL
502 lines
21 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity tri_bht is
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generic(expand_type : integer := 1 );
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port(
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gnd : inout power_logic;
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vdd : inout power_logic;
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vcs : inout power_logic;
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nclk : in clk_logic;
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pc_iu_func_sl_thold_2 : in std_ulogic;
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pc_iu_sg_2 : in std_ulogic;
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pc_iu_time_sl_thold_2 : in std_ulogic;
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pc_iu_abst_sl_thold_2 : in std_ulogic;
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pc_iu_ary_nsl_thold_2 : in std_ulogic;
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pc_iu_repr_sl_thold_2 : in std_ulogic;
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pc_iu_bolt_sl_thold_2 : in std_ulogic;
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tc_ac_ccflush_dc : in std_ulogic;
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tc_ac_scan_dis_dc_b : in std_ulogic;
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clkoff_b : in std_ulogic;
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scan_diag_dc : in std_ulogic;
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act_dis : in std_ulogic;
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d_mode : in std_ulogic;
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delay_lclkr : in std_ulogic;
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mpw1_b : in std_ulogic;
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mpw2_b : in std_ulogic;
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g8t_clkoff_b : in std_ulogic;
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g8t_d_mode : in std_ulogic;
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g8t_delay_lclkr : in std_ulogic_vector(0 to 4);
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g8t_mpw1_b : in std_ulogic_vector(0 to 4);
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g8t_mpw2_b : in std_ulogic;
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func_scan_in : in std_ulogic;
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time_scan_in : in std_ulogic;
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abst_scan_in : in std_ulogic;
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repr_scan_in : in std_ulogic;
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func_scan_out : out std_ulogic;
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time_scan_out : out std_ulogic;
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abst_scan_out : out std_ulogic;
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repr_scan_out : out std_ulogic;
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pc_iu_abist_di_0 : in std_ulogic_vector(0 to 3);
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pc_iu_abist_g8t_bw_1 : in std_ulogic;
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pc_iu_abist_g8t_bw_0 : in std_ulogic;
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pc_iu_abist_waddr_0 : in std_ulogic_vector(3 to 9);
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pc_iu_abist_g8t_wenb : in std_ulogic;
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pc_iu_abist_raddr_0 : in std_ulogic_vector(3 to 9);
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pc_iu_abist_g8t1p_renb_0 : in std_ulogic;
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an_ac_lbist_ary_wrt_thru_dc: in std_ulogic;
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pc_iu_abist_ena_dc : in std_ulogic;
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pc_iu_abist_wl128_comp_ena : in std_ulogic;
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pc_iu_abist_raw_dc_b : in std_ulogic;
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pc_iu_abist_g8t_dcomp : in std_ulogic_vector(0 to 3);
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pc_iu_bo_enable_2 : in std_ulogic;
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pc_iu_bo_reset : in std_ulogic;
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pc_iu_bo_unload : in std_ulogic;
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pc_iu_bo_repair : in std_ulogic;
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pc_iu_bo_shdata : in std_ulogic;
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pc_iu_bo_select : in std_ulogic;
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iu_pc_bo_fail : out std_ulogic;
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iu_pc_bo_diagout : out std_ulogic;
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r_act : in std_ulogic;
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w_act : in std_ulogic_vector(0 to 3);
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r_addr : in std_ulogic_vector(0 to 7);
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w_addr : in std_ulogic_vector(0 to 7);
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data_in : in std_ulogic_vector(0 to 1);
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data_out0 : out std_ulogic_vector(0 to 1);
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data_out1 : out std_ulogic_vector(0 to 1);
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data_out2 : out std_ulogic_vector(0 to 1);
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data_out3 : out std_ulogic_vector(0 to 1)
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);
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-- pragma translate_off
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-- pragma translate_on
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end tri_bht;
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architecture tri_bht of tri_bht is
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constant data_in_offset : natural := 0;
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constant w_act_offset : natural := data_in_offset + 2;
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constant r_act_offset : natural := w_act_offset + 4;
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constant w_addr_offset : natural := r_act_offset + 1;
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constant r_addr_offset : natural := w_addr_offset + 8;
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constant data_out_offset : natural := r_addr_offset + 8;
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constant array_offset : natural := data_out_offset + 8;
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constant scan_right : natural := array_offset + 1 - 1;
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constant INIT_MASK : std_ulogic_vector(0 to 1) := "10";
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signal pc_iu_func_sl_thold_1 : std_ulogic;
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signal pc_iu_func_sl_thold_0 : std_ulogic;
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signal pc_iu_func_sl_thold_0_b : std_ulogic;
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signal pc_iu_time_sl_thold_1 : std_ulogic;
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signal pc_iu_time_sl_thold_0 : std_ulogic;
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signal pc_iu_ary_nsl_thold_1 : std_ulogic;
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signal pc_iu_ary_nsl_thold_0 : std_ulogic;
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signal pc_iu_abst_sl_thold_1 : std_ulogic;
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signal pc_iu_abst_sl_thold_0 : std_ulogic;
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signal pc_iu_repr_sl_thold_1 : std_ulogic;
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signal pc_iu_repr_sl_thold_0 : std_ulogic;
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signal pc_iu_bolt_sl_thold_1 : std_ulogic;
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signal pc_iu_bolt_sl_thold_0 : std_ulogic;
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signal pc_iu_sg_1 : std_ulogic;
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signal pc_iu_sg_0 : std_ulogic;
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signal forcee : std_ulogic;
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signal siv : std_ulogic_vector(0 to scan_right);
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signal sov : std_ulogic_vector(0 to scan_right);
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signal tiup : std_ulogic;
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signal data_out_d : std_ulogic_vector(0 to 7);
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signal data_out_q : std_ulogic_vector(0 to 7);
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signal ary_w_en : std_ulogic;
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signal ary_w_addr : std_ulogic_vector(0 to 6);
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signal ary_w_sel : std_ulogic_vector(0 to 15);
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signal ary_w_data : std_ulogic_vector(0 to 15);
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signal ary_r_en : std_ulogic;
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signal ary_r_addr : std_ulogic_vector(0 to 6);
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signal ary_r_data : std_ulogic_vector(0 to 15);
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signal data_out : std_ulogic_vector(0 to 7);
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signal write_thru : std_ulogic_vector(0 to 3);
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signal data_in_d : std_ulogic_vector(0 to 1);
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signal data_in_q : std_ulogic_vector(0 to 1);
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signal w_act_d : std_ulogic_vector(0 to 3);
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signal w_act_q : std_ulogic_vector(0 to 3);
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signal r_act_d : std_ulogic;
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signal r_act_q : std_ulogic;
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signal w_addr_d : std_ulogic_vector(0 to 7);
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signal w_addr_q : std_ulogic_vector(0 to 7);
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signal r_addr_d : std_ulogic_vector(0 to 7);
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signal r_addr_q : std_ulogic_vector(0 to 7);
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begin
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tiup <= '1';
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data_out0(0 to 1) <= data_out_q(0 to 1);
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data_out1(0 to 1) <= data_out_q(2 to 3);
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data_out2(0 to 1) <= data_out_q(4 to 5);
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data_out3(0 to 1) <= data_out_q(6 to 7);
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ary_w_en <= or_reduce(w_act(0 to 3)) and not ((w_addr(1 to 7) = r_addr(1 to 7)) and r_act = '1');
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ary_w_addr(0 to 6) <= w_addr(1 to 7);
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ary_w_sel(0) <= w_act(0) and w_addr(0) = '0';
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ary_w_sel(1) <= w_act(0) and w_addr(0) = '0';
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ary_w_sel(2) <= w_act(1) and w_addr(0) = '0';
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ary_w_sel(3) <= w_act(1) and w_addr(0) = '0';
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ary_w_sel(4) <= w_act(2) and w_addr(0) = '0';
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ary_w_sel(5) <= w_act(2) and w_addr(0) = '0';
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ary_w_sel(6) <= w_act(3) and w_addr(0) = '0';
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ary_w_sel(7) <= w_act(3) and w_addr(0) = '0';
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ary_w_sel(8) <= w_act(0) and w_addr(0) = '1';
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ary_w_sel(9) <= w_act(0) and w_addr(0) = '1';
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ary_w_sel(10) <= w_act(1) and w_addr(0) = '1';
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ary_w_sel(11) <= w_act(1) and w_addr(0) = '1';
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ary_w_sel(12) <= w_act(2) and w_addr(0) = '1';
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ary_w_sel(13) <= w_act(2) and w_addr(0) = '1';
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ary_w_sel(14) <= w_act(3) and w_addr(0) = '1';
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ary_w_sel(15) <= w_act(3) and w_addr(0) = '1';
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ary_w_data(0 to 15) <= (data_in(0 to 1) xor INIT_MASK(0 to 1)) &
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(data_in(0 to 1) xor INIT_MASK(0 to 1)) &
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(data_in(0 to 1) xor INIT_MASK(0 to 1)) &
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(data_in(0 to 1) xor INIT_MASK(0 to 1)) &
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(data_in(0 to 1) xor INIT_MASK(0 to 1)) &
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(data_in(0 to 1) xor INIT_MASK(0 to 1)) &
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(data_in(0 to 1) xor INIT_MASK(0 to 1)) &
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(data_in(0 to 1) xor INIT_MASK(0 to 1)) ;
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ary_r_en <= r_act;
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ary_r_addr(0 to 6) <= r_addr(1 to 7);
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data_out(0 to 7) <= gate(ary_r_data(0 to 7) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '0') or
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gate(ary_r_data(8 to 15) xor (INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1) & INIT_MASK(0 to 1)), r_addr_q(0) = '1') ;
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data_in_d(0 to 1) <= data_in(0 to 1);
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w_act_d(0 to 3) <= w_act(0 to 3);
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r_act_d <= r_act;
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w_addr_d(0 to 7) <= w_addr(0 to 7);
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r_addr_d(0 to 7) <= r_addr(0 to 7);
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write_thru(0 to 3) <= w_act_q(0 to 3) when (w_addr_q(0 to 7) = r_addr_q(0 to 7)) and r_act_q = '1' else "0000";
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data_out_d(0 to 1) <= data_in_q(0 to 1) when write_thru(0) = '1' else
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data_out(0 to 1);
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data_out_d(2 to 3) <= data_in_q(0 to 1) when write_thru(1) = '1' else
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data_out(2 to 3);
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data_out_d(4 to 5) <= data_in_q(0 to 1) when write_thru(2) = '1' else
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data_out(4 to 5);
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data_out_d(6 to 7) <= data_in_q(0 to 1) when write_thru(3) = '1' else
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data_out(6 to 7);
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bht0: entity tri.tri_128x16_1r1w_1
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generic map ( expand_type => expand_type )
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port map(
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gnd => gnd,
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vdd => vdd,
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vcs => vcs,
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nclk => nclk,
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rd_act => ary_r_en,
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wr_act => ary_w_en,
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lcb_d_mode_dc => g8t_d_mode,
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lcb_clkoff_dc_b => g8t_clkoff_b,
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lcb_mpw1_dc_b => g8t_mpw1_b,
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lcb_mpw2_dc_b => g8t_mpw2_b,
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lcb_delay_lclkr_dc => g8t_delay_lclkr,
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ccflush_dc => tc_ac_ccflush_dc,
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scan_dis_dc_b => tc_ac_scan_dis_dc_b,
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scan_diag_dc => scan_diag_dc,
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func_scan_in => siv(array_offset),
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func_scan_out => sov(array_offset),
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lcb_sg_0 => pc_iu_sg_0,
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lcb_sl_thold_0_b => pc_iu_func_sl_thold_0_b,
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lcb_time_sl_thold_0 => pc_iu_time_sl_thold_0,
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lcb_abst_sl_thold_0 => pc_iu_abst_sl_thold_0,
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lcb_ary_nsl_thold_0 => pc_iu_ary_nsl_thold_0,
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lcb_repr_sl_thold_0 => pc_iu_repr_sl_thold_0,
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time_scan_in => time_scan_in,
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time_scan_out => time_scan_out,
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abst_scan_in => abst_scan_in,
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abst_scan_out => abst_scan_out,
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repr_scan_in => repr_scan_in,
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repr_scan_out => repr_scan_out,
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abist_di => pc_iu_abist_di_0,
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abist_bw_odd => pc_iu_abist_g8t_bw_1,
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abist_bw_even => pc_iu_abist_g8t_bw_0,
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abist_wr_adr => pc_iu_abist_waddr_0,
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wr_abst_act => pc_iu_abist_g8t_wenb,
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abist_rd0_adr => pc_iu_abist_raddr_0,
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rd0_abst_act => pc_iu_abist_g8t1p_renb_0,
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tc_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc,
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abist_ena_1 => pc_iu_abist_ena_dc,
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abist_g8t_rd0_comp_ena => pc_iu_abist_wl128_comp_ena,
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abist_raw_dc_b => pc_iu_abist_raw_dc_b,
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obs0_abist_cmp => pc_iu_abist_g8t_dcomp,
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lcb_bolt_sl_thold_0 => pc_iu_bolt_sl_thold_0,
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pc_bo_enable_2 => pc_iu_bo_enable_2,
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pc_bo_reset => pc_iu_bo_reset,
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pc_bo_unload => pc_iu_bo_unload,
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pc_bo_repair => pc_iu_bo_repair,
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pc_bo_shdata => pc_iu_bo_shdata,
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pc_bo_select => pc_iu_bo_select,
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bo_pc_failout => iu_pc_bo_fail,
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bo_pc_diagloop => iu_pc_bo_diagout,
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tri_lcb_mpw1_dc_b => mpw1_b,
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tri_lcb_mpw2_dc_b => mpw2_b,
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tri_lcb_delay_lclkr_dc => delay_lclkr,
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tri_lcb_clkoff_dc_b => clkoff_b,
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tri_lcb_act_dis_dc => act_dis,
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bw => ary_w_sel,
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wr_adr => ary_w_addr,
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rd_adr => ary_r_addr,
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di => ary_w_data,
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do => ary_r_data
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);
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data_in_reg: tri_rlmreg_p
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generic map (width => data_in_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(data_in_offset to data_in_offset + data_in_q'length-1),
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scout => sov(data_in_offset to data_in_offset + data_in_q'length-1),
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din => data_in_d,
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dout => data_in_q);
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w_act_reg: tri_rlmreg_p
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generic map (width => w_act_q'length, init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(w_act_offset to w_act_offset + w_act_q'length-1),
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scout => sov(w_act_offset to w_act_offset + w_act_q'length-1),
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din => w_act_d,
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dout => w_act_q);
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r_act_reg: tri_rlmlatch_p
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generic map (init => 0, expand_type => expand_type)
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port map (vd => vdd,
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gd => gnd,
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nclk => nclk,
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act => tiup,
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thold_b => pc_iu_func_sl_thold_0_b,
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sg => pc_iu_sg_0,
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forcee => forcee,
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delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b,
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mpw2_b => mpw2_b,
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d_mode => d_mode,
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scin => siv(r_act_offset),
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scout => sov(r_act_offset),
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din => r_act_d,
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dout => r_act_q);
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|
|
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w_addr_reg: tri_rlmreg_p
|
|
generic map (width => w_addr_q'length, init => 0, expand_type => expand_type)
|
|
port map (vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
act => tiup,
|
|
thold_b => pc_iu_func_sl_thold_0_b,
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|
sg => pc_iu_sg_0,
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr,
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|
mpw1_b => mpw1_b,
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|
mpw2_b => mpw2_b,
|
|
d_mode => d_mode,
|
|
scin => siv(w_addr_offset to w_addr_offset + w_addr_q'length-1),
|
|
scout => sov(w_addr_offset to w_addr_offset + w_addr_q'length-1),
|
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din => w_addr_d,
|
|
dout => w_addr_q);
|
|
|
|
r_addr_reg: tri_rlmreg_p
|
|
generic map (width => r_addr_q'length, init => 0, expand_type => expand_type)
|
|
port map (vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
act => tiup,
|
|
thold_b => pc_iu_func_sl_thold_0_b,
|
|
sg => pc_iu_sg_0,
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr,
|
|
mpw1_b => mpw1_b,
|
|
mpw2_b => mpw2_b,
|
|
d_mode => d_mode,
|
|
scin => siv(r_addr_offset to r_addr_offset + r_addr_q'length-1),
|
|
scout => sov(r_addr_offset to r_addr_offset + r_addr_q'length-1),
|
|
din => r_addr_d,
|
|
dout => r_addr_q);
|
|
|
|
|
|
data_out_reg: tri_rlmreg_p
|
|
generic map (width => data_out_q'length, init => 0, expand_type => expand_type)
|
|
port map (vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
act => tiup,
|
|
thold_b => pc_iu_func_sl_thold_0_b,
|
|
sg => pc_iu_sg_0,
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr,
|
|
mpw1_b => mpw1_b,
|
|
mpw2_b => mpw2_b,
|
|
d_mode => d_mode,
|
|
scin => siv(data_out_offset to data_out_offset + data_out_q'length-1),
|
|
scout => sov(data_out_offset to data_out_offset + data_out_q'length-1),
|
|
din => data_out_d,
|
|
dout => data_out_q);
|
|
|
|
|
|
|
|
perv_2to1_reg: tri_plat
|
|
generic map (width => 7, expand_type => expand_type)
|
|
port map (vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
flush => tc_ac_ccflush_dc,
|
|
din(0) => pc_iu_func_sl_thold_2,
|
|
din(1) => pc_iu_sg_2,
|
|
din(2) => pc_iu_time_sl_thold_2,
|
|
din(3) => pc_iu_abst_sl_thold_2,
|
|
din(4) => pc_iu_ary_nsl_thold_2,
|
|
din(5) => pc_iu_repr_sl_thold_2,
|
|
din(6) => pc_iu_bolt_sl_thold_2,
|
|
q(0) => pc_iu_func_sl_thold_1,
|
|
q(1) => pc_iu_sg_1,
|
|
q(2) => pc_iu_time_sl_thold_1,
|
|
q(3) => pc_iu_abst_sl_thold_1,
|
|
q(4) => pc_iu_ary_nsl_thold_1,
|
|
q(5) => pc_iu_repr_sl_thold_1,
|
|
q(6) => pc_iu_bolt_sl_thold_1
|
|
);
|
|
|
|
perv_1to0_reg: tri_plat
|
|
generic map (width => 7, expand_type => expand_type)
|
|
port map (vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
flush => tc_ac_ccflush_dc,
|
|
din(0) => pc_iu_func_sl_thold_1,
|
|
din(1) => pc_iu_sg_1,
|
|
din(2) => pc_iu_time_sl_thold_1,
|
|
din(3) => pc_iu_abst_sl_thold_1,
|
|
din(4) => pc_iu_ary_nsl_thold_1,
|
|
din(5) => pc_iu_repr_sl_thold_1,
|
|
din(6) => pc_iu_bolt_sl_thold_1,
|
|
q(0) => pc_iu_func_sl_thold_0,
|
|
q(1) => pc_iu_sg_0,
|
|
q(2) => pc_iu_time_sl_thold_0,
|
|
q(3) => pc_iu_abst_sl_thold_0,
|
|
q(4) => pc_iu_ary_nsl_thold_0,
|
|
q(5) => pc_iu_repr_sl_thold_0,
|
|
q(6) => pc_iu_bolt_sl_thold_0
|
|
);
|
|
|
|
perv_lcbor: tri_lcbor
|
|
generic map (expand_type => expand_type)
|
|
port map (clkoff_b => clkoff_b,
|
|
thold => pc_iu_func_sl_thold_0,
|
|
sg => pc_iu_sg_0,
|
|
act_dis => act_dis,
|
|
forcee => forcee,
|
|
thold_b => pc_iu_func_sl_thold_0_b);
|
|
|
|
|
|
|
|
siv(0 to scan_right) <= func_scan_in & sov(0 to scan_right-1);
|
|
func_scan_out <= sov(scan_right);
|
|
|
|
|
|
end tri_bht;
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