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179 lines
8.5 KiB
VHDL
179 lines
8.5 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_function_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri;
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use tri.tri_latches_pkg.all;
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entity tri_cam_parerr_mac is
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generic (expand_type : integer := 1);
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port(
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np1_cam_cmp_data :in std_ulogic_vector(0 to 83);
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np1_array_cmp_data :in std_ulogic_vector(0 to 67);
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np2_cam_cmp_data :out std_ulogic_vector(0 to 83);
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np2_array_cmp_data :out std_ulogic_vector(0 to 67);
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np2_cmp_data_parerr_epn :out std_ulogic;
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np2_cmp_data_parerr_rpn :out std_ulogic;
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gnd :inout power_logic;
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vdd :inout power_logic;
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nclk :in clk_logic;
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act :in std_ulogic;
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lcb_act_dis_dc :in std_ulogic;
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lcb_delay_lclkr_dc :in std_ulogic;
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lcb_clkoff_dc_b_0 :in std_ulogic;
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lcb_mpw1_dc_b :in std_ulogic;
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lcb_mpw2_dc_b :in std_ulogic;
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lcb_sg_0 :in std_ulogic;
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lcb_func_sl_thold_0 :in std_ulogic;
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func_scan_in :in std_ulogic;
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func_scan_out :out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end entity tri_cam_parerr_mac;
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architecture tri_cam_parerr_mac of tri_cam_parerr_mac is
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begin
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um: if expand_type = 0 generate
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signal np2_cam_cmp_data_q :std_ulogic_vector(0 to np1_cam_cmp_data'length-1);
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signal np2_array_cmp_data_q :std_ulogic_vector(0 to np1_array_cmp_data'length-1);
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signal np2_cmp_data_calc_par :std_ulogic_vector(50 to 67);
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begin
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np1_cam_cmp_data_latch: tri_rlmreg_p
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generic map (width => np1_cam_cmp_data'length, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => act,
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scin => (others => '0'),
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scout => open,
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din => np1_cam_cmp_data,
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dout => np2_cam_cmp_data_q);
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np1_array_cmp_data_latch: tri_rlmreg_p
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generic map (width => np1_array_cmp_data'length, init => 0, expand_type => expand_type)
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port map (nclk => nclk,
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act => act,
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scin => (others => '0'),
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scout => open,
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din => np1_array_cmp_data,
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dout => np2_array_cmp_data_q);
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np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82));
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np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7));
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np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15));
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np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23));
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np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31));
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np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39));
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np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47));
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np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55));
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np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62));
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np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66));
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np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74));
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np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5));
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np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13));
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np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21));
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np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29));
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np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37));
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np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44));
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np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50));
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np2_cmp_data_parerr_epn <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60)));
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np2_cmp_data_parerr_rpn <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67));
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np2_cam_cmp_data <= np2_cam_cmp_data_q;
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np2_array_cmp_data <= np2_array_cmp_data_q;
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end generate um;
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a: if expand_type = 1 generate
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signal np2_cam_cmp_data_q :std_ulogic_vector(0 to np1_cam_cmp_data'length-1);
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signal np2_array_cmp_data_q :std_ulogic_vector(0 to np1_array_cmp_data'length-1);
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signal np2_cmp_data_calc_par :std_ulogic_vector(50 to 67);
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signal clk :std_ulogic;
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signal sreset_q :std_ulogic;
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begin
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clk <= not nclk.clk;
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rlatch: process (clk)
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begin
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if(rising_edge(clk)) then
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sreset_q <= nclk.sreset;
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end if;
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end process;
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slatch: process (nclk,sreset_q)
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begin
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if(rising_edge(nclk.clk)) then
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if (sreset_q = '1') then
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np2_cam_cmp_data_q <= (others=>'0');
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np2_array_cmp_data_q <= (others=>'0');
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else
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np2_cam_cmp_data_q <= np1_cam_cmp_data;
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np2_array_cmp_data_q <= np1_array_cmp_data;
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end if;
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end if;
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end process;
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np2_cmp_data_calc_par(50) <= xor_reduce(np2_cam_cmp_data_q(75 to 82));
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np2_cmp_data_calc_par(51) <= xor_reduce(np2_cam_cmp_data_q(0 to 7));
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np2_cmp_data_calc_par(52) <= xor_reduce(np2_cam_cmp_data_q(8 to 15));
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np2_cmp_data_calc_par(53) <= xor_reduce(np2_cam_cmp_data_q(16 to 23));
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np2_cmp_data_calc_par(54) <= xor_reduce(np2_cam_cmp_data_q(24 to 31));
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np2_cmp_data_calc_par(55) <= xor_reduce(np2_cam_cmp_data_q(32 to 39));
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np2_cmp_data_calc_par(56) <= xor_reduce(np2_cam_cmp_data_q(40 to 47));
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np2_cmp_data_calc_par(57) <= xor_reduce(np2_cam_cmp_data_q(48 to 55));
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np2_cmp_data_calc_par(58) <= xor_reduce(np2_cam_cmp_data_q(57 to 62));
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np2_cmp_data_calc_par(59) <= xor_reduce(np2_cam_cmp_data_q(63 to 66));
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np2_cmp_data_calc_par(60) <= xor_reduce(np2_cam_cmp_data_q(67 to 74));
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np2_cmp_data_calc_par(61) <= xor_reduce(np2_array_cmp_data_q(0 to 5));
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np2_cmp_data_calc_par(62) <= xor_reduce(np2_array_cmp_data_q(6 to 13));
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np2_cmp_data_calc_par(63) <= xor_reduce(np2_array_cmp_data_q(14 to 21));
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np2_cmp_data_calc_par(64) <= xor_reduce(np2_array_cmp_data_q(22 to 29));
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np2_cmp_data_calc_par(65) <= xor_reduce(np2_array_cmp_data_q(30 to 37));
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np2_cmp_data_calc_par(66) <= xor_reduce(np2_array_cmp_data_q(38 to 44));
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np2_cmp_data_calc_par(67) <= xor_reduce(np2_array_cmp_data_q(45 to 50));
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np2_cmp_data_parerr_epn <= or_reduce(np2_cmp_data_calc_par(50 to 60) xor (np2_cam_cmp_data_q(83) & np2_array_cmp_data_q(51 to 60)));
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np2_cmp_data_parerr_rpn <= or_reduce(np2_cmp_data_calc_par(61 to 67) xor np2_array_cmp_data_q(61 to 67));
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np2_cam_cmp_data <= np2_cam_cmp_data_q;
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np2_array_cmp_data <= np2_array_cmp_data_q;
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func_scan_out <= func_scan_in;
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end generate a;
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end tri_cam_parerr_mac;
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