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120 lines
4.5 KiB
VHDL
120 lines
4.5 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library support;
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use support.power_logic_pkg.all;
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library tri; use tri.tri_latches_pkg.all;
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entity tri_inv_nlats is
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generic (
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offset : natural range 0 to 65535 := 0;
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width : positive range 1 to 65536 := 1 ;
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init : std_ulogic_vector := "0" ;
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synthclonedlatch : string := "" ;
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btr : string := "NLI0001_X1_A12TH" ;
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needs_sreset : integer := 1 ;
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expand_type : integer := 1 );
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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LCLK : in clk_logic;
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D1CLK : in std_ulogic;
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D2CLK : in std_ulogic;
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SCANIN : in std_ulogic_vector(offset to offset+width-1);
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SCANOUT : out std_ulogic_vector(offset to offset+width-1);
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D : in std_ulogic_vector(offset to offset+width-1);
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QB : out std_ulogic_vector(offset to offset+width-1)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end entity tri_inv_nlats;
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architecture tri_inv_nlats of tri_inv_nlats is
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begin
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a: if expand_type = 1 generate
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constant init_v : std_ulogic_vector(0 to (init'length + width-1)):=init & (0 to width-1=>'0');
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constant zeros : std_ulogic_vector(0 to width-1) := (0 to width-1 => '0');
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signal sreset : std_ulogic;
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signal int_din : std_ulogic_vector(0 to width-1);
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signal int_dout : std_ulogic_vector(0 to width-1) := init_v(0 to width-1);
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signal vact, vact_b : std_ulogic_vector(0 to width-1);
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signal vsreset, vsreset_b : std_ulogic_vector(0 to width-1);
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signal vthold, vthold_b : std_ulogic_vector(0 to width-1);
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signal din : std_ulogic_vector(0 to width-1);
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signal unused : std_ulogic_vector(0 to width-1);
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-- synopsys translate_off
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-- synopsys translate_on
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begin
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rst: if needs_sreset = 1 generate
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sreset <= LCLK.sreset;
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end generate rst;
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no_rst: if needs_sreset /=1 generate
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sreset <= '0';
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end generate no_rst;
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vsreset <= (0 to width-1 => sreset);
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vsreset_b <= (0 to width-1 => not sreset);
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din <= D ;
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int_din <= (vsreset_b and din) or
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(vsreset and init_v(0 to width-1));
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vact <= (0 to width-1 => D1CLK);
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vact_b <= (0 to width-1 => not D1CLK);
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vthold_b <= (0 to width-1 => D2CLK);
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vthold <= (0 to width-1 => not D2CLK);
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l: process (LCLK, vact, int_din, vact_b, int_dout, vsreset, vsreset_b, vthold_b, vthold)
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begin
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if rising_edge(LCLK.clk) then
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int_dout <= (((vact and vthold_b) or vsreset) and int_din) or
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(((vact_b or vthold) and vsreset_b) and int_dout);
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end if;
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end process l;
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QB <= not int_dout;
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SCANOUT <= zeros;
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unused <= SCANIN;
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end generate a;
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end tri_inv_nlats;
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