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101 lines
3.9 KiB
VHDL
101 lines
3.9 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri;
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use ieee.std_logic_1164.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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entity tri_ser_rlmreg_p is
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generic (
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width : positive range 1 to 65536 := 1 ;
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offset : natural range 0 to 65535 := 0 ;
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init : integer := 0;
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ibuf : boolean := false;
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dualscan : string := "";
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needs_sreset : integer := 1 ;
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expand_type : integer := 1 );
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port (
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vd : inout power_logic;
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gd : inout power_logic;
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nclk : in clk_logic;
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act : in std_ulogic := '1';
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forcee : in std_ulogic := '0';
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thold_b : in std_ulogic := '1';
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d_mode : in std_ulogic := '0';
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sg : in std_ulogic := '0';
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delay_lclkr : in std_ulogic := '0';
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mpw1_b : in std_ulogic := '1';
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mpw2_b : in std_ulogic := '1';
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scin : in std_ulogic_vector(offset to offset+width-1);
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din : in std_ulogic_vector(offset to offset+width-1);
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scout : out std_ulogic_vector(offset to offset+width-1);
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dout : out std_ulogic_vector(offset to offset+width-1));
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-- synopsys translate_off
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-- synopsys translate_on
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end entity tri_ser_rlmreg_p;
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architecture tri_ser_rlmreg_p of tri_ser_rlmreg_p is
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signal dout_b, act_buf, act_buf_b, dout_buf : std_ulogic_vector(offset to offset+width-1);
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begin
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act_buf <= (others=>act);
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act_buf_b <= (others=>not(act));
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dout_buf <= not dout_b;
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dout <= dout_buf;
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tri_ser_rlmreg_p : entity tri.tri_aoi22_nlats_wlcb(tri_aoi22_nlats_wlcb)
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generic map (
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width => width,
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offset => offset,
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init => init,
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ibuf => ibuf,
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dualscan=> dualscan,
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expand_type => expand_type,
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needs_sreset => needs_sreset)
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port map (nclk => nclk, vd => vd, gd => gd,
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act => act,
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forcee => forcee,
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d_mode => d_mode, delay_lclkr => delay_lclkr,
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mpw1_b => mpw1_b, mpw2_b => mpw2_b,
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thold_b => thold_b,
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sg => sg,
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scin => scin,
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scout => scout,
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A1 => din,
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A2 => act_buf,
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B1 => dout_buf,
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B2 => act_buf_b,
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QB => dout_b);
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end tri_ser_rlmreg_p;
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