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125 lines
5.2 KiB
VHDL
125 lines
5.2 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all ;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity fuq_add_all1 is port(
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ex3_inc_byt_c_b :in std_ulogic_vector(0 to 6);
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ex3_inc_byt_c_glb :out std_ulogic_vector(1 to 6);
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ex3_inc_byt_c_glb_b :out std_ulogic_vector(1 to 6);
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ex3_inc_all1 :out std_ulogic
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);
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END fuq_add_all1;
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ARCHITECTURE fuq_add_all1 OF fuq_add_all1 IS
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal ex3_inc_byt_g1 :std_ulogic_vector(0 to 6);
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signal ex3_inc_byt_g2_b :std_ulogic_vector(0 to 6);
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signal ex3_inc_byt_g4 :std_ulogic_vector(0 to 6);
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signal ex3_inc_byt_g8_b :std_ulogic_vector(0 to 6);
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signal ex3_inc_byt_g_glb_int :std_ulogic_vector(1 to 6);
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BEGIN
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ii: ex3_inc_byt_g1(0 to 6) <= not ex3_inc_byt_c_b(0 to 6);
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g26: ex3_inc_byt_g2_b(6) <= not( ex3_inc_byt_g1(6) );
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g25: ex3_inc_byt_g2_b(5) <= not( ex3_inc_byt_g1(5) and ex3_inc_byt_g1(6) );
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g24: ex3_inc_byt_g2_b(4) <= not( ex3_inc_byt_g1(4) and ex3_inc_byt_g1(5) );
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g23: ex3_inc_byt_g2_b(3) <= not( ex3_inc_byt_g1(3) and ex3_inc_byt_g1(4) );
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g22: ex3_inc_byt_g2_b(2) <= not( ex3_inc_byt_g1(2) and ex3_inc_byt_g1(3) );
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g21: ex3_inc_byt_g2_b(1) <= not( ex3_inc_byt_g1(1) and ex3_inc_byt_g1(2) );
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g20: ex3_inc_byt_g2_b(0) <= not( ex3_inc_byt_g1(0) and ex3_inc_byt_g1(1) );
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g46: ex3_inc_byt_g4(6) <= not( ex3_inc_byt_g2_b(6) );
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g45: ex3_inc_byt_g4(5) <= not( ex3_inc_byt_g2_b(5) );
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g44: ex3_inc_byt_g4(4) <= not( ex3_inc_byt_g2_b(4) or ex3_inc_byt_g2_b(6) );
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g43: ex3_inc_byt_g4(3) <= not( ex3_inc_byt_g2_b(3) or ex3_inc_byt_g2_b(5) );
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g42: ex3_inc_byt_g4(2) <= not( ex3_inc_byt_g2_b(2) or ex3_inc_byt_g2_b(4) );
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g41: ex3_inc_byt_g4(1) <= not( ex3_inc_byt_g2_b(1) or ex3_inc_byt_g2_b(3) );
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g40: ex3_inc_byt_g4(0) <= not( ex3_inc_byt_g2_b(0) or ex3_inc_byt_g2_b(2) );
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g86: ex3_inc_byt_g8_b(6) <= not( ex3_inc_byt_g4(6) );
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g85: ex3_inc_byt_g8_b(5) <= not( ex3_inc_byt_g4(5) );
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g84: ex3_inc_byt_g8_b(4) <= not( ex3_inc_byt_g4(4) );
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g83: ex3_inc_byt_g8_b(3) <= not( ex3_inc_byt_g4(3) );
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g82: ex3_inc_byt_g8_b(2) <= not( ex3_inc_byt_g4(2) and ex3_inc_byt_g4(6) );
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g81: ex3_inc_byt_g8_b(1) <= not( ex3_inc_byt_g4(1) and ex3_inc_byt_g4(5) );
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g80: ex3_inc_byt_g8_b(0) <= not( ex3_inc_byt_g4(0) and ex3_inc_byt_g4(4) );
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all1: ex3_inc_all1 <= not ex3_inc_byt_g8_b(0);
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iop1: ex3_inc_byt_c_glb(1) <= not ex3_inc_byt_g8_b(1);
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iop2: ex3_inc_byt_c_glb(2) <= not ex3_inc_byt_g8_b(2);
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iop3: ex3_inc_byt_c_glb(3) <= not ex3_inc_byt_g8_b(3);
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iop4: ex3_inc_byt_c_glb(4) <= not ex3_inc_byt_g8_b(4);
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iop5: ex3_inc_byt_c_glb(5) <= not ex3_inc_byt_g8_b(5);
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iop6: ex3_inc_byt_c_glb(6) <= not ex3_inc_byt_g8_b(6);
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ionn1: ex3_inc_byt_g_glb_int(1) <= not ex3_inc_byt_g8_b(1);
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ionn2: ex3_inc_byt_g_glb_int(2) <= not ex3_inc_byt_g8_b(2);
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ionn3: ex3_inc_byt_g_glb_int(3) <= not ex3_inc_byt_g8_b(3);
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ionn4: ex3_inc_byt_g_glb_int(4) <= not ex3_inc_byt_g8_b(4);
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ionn5: ex3_inc_byt_g_glb_int(5) <= not ex3_inc_byt_g8_b(5);
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ionn6: ex3_inc_byt_g_glb_int(6) <= not ex3_inc_byt_g8_b(6);
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ion1: ex3_inc_byt_c_glb_b(1) <= not ex3_inc_byt_g_glb_int(1) ;
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ion2: ex3_inc_byt_c_glb_b(2) <= not ex3_inc_byt_g_glb_int(2) ;
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ion3: ex3_inc_byt_c_glb_b(3) <= not ex3_inc_byt_g_glb_int(3) ;
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ion4: ex3_inc_byt_c_glb_b(4) <= not ex3_inc_byt_g_glb_int(4) ;
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ion5: ex3_inc_byt_c_glb_b(5) <= not ex3_inc_byt_g_glb_int(5) ;
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ion6: ex3_inc_byt_c_glb_b(6) <= not ex3_inc_byt_g_glb_int(6) ;
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END;
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