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112 lines
4.2 KiB
VHDL
112 lines
4.2 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity fuq_alg_bypmux is
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generic( expand_type : integer := 2 );
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port(
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ex2_byp_sel_byp_neg :in std_ulogic;
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ex2_byp_sel_byp_pos :in std_ulogic;
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ex2_byp_sel_neg :in std_ulogic;
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ex2_byp_sel_pos :in std_ulogic;
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ex2_prd_sel_neg_hi :in std_ulogic;
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ex2_prd_sel_neg_lo :in std_ulogic;
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ex2_prd_sel_neg_lohi :in std_ulogic;
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ex2_prd_sel_pos_hi :in std_ulogic;
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ex2_prd_sel_pos_lo :in std_ulogic;
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ex2_prd_sel_pos_lohi :in std_ulogic;
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ex2_sh_lvl3 :in std_ulogic_vector(0 to 162);
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f_fmt_ex2_pass_frac :in std_ulogic_vector(0 to 52);
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f_alg_ex2_res :out std_ulogic_vector(0 to 162)
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);
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end fuq_alg_bypmux;
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architecture fuq_alg_bypmux of fuq_alg_bypmux is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal m0_b, m1_b :std_ulogic_vector(0 to 162);
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signal ex2_sh_lvl3_b :std_ulogic_vector(0 to 162);
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signal f_fmt_ex2_pass_frac_b :std_ulogic_vector(0 to 52);
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begin
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i0: ex2_sh_lvl3_b(0 to 162) <= not( ex2_sh_lvl3(0 to 162) );
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i1: f_fmt_ex2_pass_frac_b(0 to 52) <= not( f_fmt_ex2_pass_frac(0 to 52) );
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m0_000: m0_b(0 to 52) <= not( ( (0 to 52=> ex2_byp_sel_pos) and ex2_sh_lvl3 (0 to 52) ) or
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( (0 to 52=> ex2_byp_sel_neg) and ex2_sh_lvl3_b (0 to 52) ) );
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m1_000: m1_b(0 to 52) <= not( ( (0 to 52=> ex2_byp_sel_byp_pos) and f_fmt_ex2_pass_frac (0 to 52) ) or
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( (0 to 52=> ex2_byp_sel_byp_neg) and f_fmt_ex2_pass_frac_b(0 to 52) ) );
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m0_053: m0_b(53 to 98) <= not( (53 to 98=> ex2_prd_sel_pos_hi) and ex2_sh_lvl3 (53 to 98) );
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m1_053: m1_b(53 to 98) <= not( (53 to 98=> ex2_prd_sel_neg_hi) and ex2_sh_lvl3_b(53 to 98) );
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m0_099: m0_b(99 to 130) <= not( (99 to 130=> ex2_prd_sel_pos_lohi) and ex2_sh_lvl3 (99 to 130) );
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m1_099: m1_b(99 to 130) <= not( (99 to 130=> ex2_prd_sel_neg_lohi) and ex2_sh_lvl3_b(99 to 130) );
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m0_131: m0_b(131 to 162) <= not( (131 to 162=> ex2_prd_sel_pos_lo) and ex2_sh_lvl3 (131 to 162) );
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m1_131: m1_b(131 to 162) <= not( (131 to 162=> ex2_prd_sel_neg_lo) and ex2_sh_lvl3_b(131 to 162) );
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mx: f_alg_ex2_res(0 to 162) <= not( m0_b(0 to 162) and m1_b(0 to 162 ) );
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end;
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