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154 lines
6.1 KiB
VHDL
154 lines
6.1 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all ;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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library support;
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use support.power_logic_pkg.all;
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library tri; use tri.tri_latches_pkg.all;
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entity fuq_gst_loa is
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port(
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a :in std_ulogic_vector(1 to 19);
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shamt :out std_ulogic_vector(0 to 4)
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);
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end fuq_gst_loa;
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architecture fuq_gst_loa of fuq_gst_loa is
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signal unused :std_ulogic;
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begin
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unused <= a(19) ;
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shamt(0) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13)
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and not a(14) and not a(15) and a(19)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14)
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and not a(15) and a(18)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14)
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and not a(15) and a(17)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and not a(08) and not a(09) and not a(10) and not a(11) and not a(12) and not a(13) and not a(14)
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and not a(15) and a(16));
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shamt(1) <= (not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(15)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(14)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(13)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(12)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(11)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(10)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(09)) or
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(not a(01) and not a(02) and not a(03) and not a(04) and not a(05) and not a(06) and not a(07)
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and a(08));
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shamt(2) <= (not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
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and a(15)) or
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(not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
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and a(14)) or
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(not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
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and a(13)) or
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(not a(01) and not a(02) and not a(03) and not a(08) and not a(09) and not a(10) and not a(11)
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and a(12)) or
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(not a(01) and not a(02) and not a(03) and a(07)) or
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(not a(01) and not a(02) and not a(03) and a(06)) or
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(not a(01) and not a(02) and not a(03) and a(05)) or
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(not a(01) and not a(02) and not a(03) and a(04));
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shamt(3) <= (not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
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and not a(16) and not a(17) and a(19)) or
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(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
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and not a(16) and not a(17) and a(18)) or
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(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
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and a(15)) or
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(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and not a(12) and not a(13)
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and a(14)) or
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(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and a(11)) or
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(not a(01) and not a(04) and not a(05) and not a(08) and not a(09) and a(10)) or
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(not a(01) and not a(04) and not a(05) and a(07)) or
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(not a(01) and not a(04) and not a(05) and a(06)) or
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(not a(01) and a(03)) or
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(not a(01) and a(02));
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shamt(4) <= (not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14)
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and not a(16) and not a(18) and a(19)) or
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(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14)
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and not a(16) and a(17)) or
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(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and not a(14)
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and a(15)) or
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(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and not a(12) and a(13)) or
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(not a(02) and not a(04) and not a(06) and not a(08) and not a(10) and a(11)) or
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(not a(02) and not a(04) and not a(06) and not a(08) and a(09)) or
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(not a(02) and not a(04) and not a(06) and a(07)) or
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(not a(02) and not a(04) and a(05)) or
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(not a(02) and a(03)) or
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( a(01));
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end fuq_gst_loa;
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