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561 lines
27 KiB
VHDL
561 lines
27 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity fuq_nrm is
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generic( expand_type : integer := 2 );
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port(
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vdd :inout power_logic;
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gnd :inout power_logic;
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clkoff_b :in std_ulogic;
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act_dis :in std_ulogic;
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flush :in std_ulogic;
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delay_lclkr :in std_ulogic_vector(4 to 5);
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mpw1_b :in std_ulogic_vector(4 to 5);
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mpw2_b :in std_ulogic_vector(0 to 1);
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sg_1 :in std_ulogic;
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thold_1 :in std_ulogic;
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fpu_enable :in std_ulogic;
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nclk :in clk_logic;
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f_nrm_si :in std_ulogic ;
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f_nrm_so :out std_ulogic ;
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ex3_act_b :in std_ulogic ;
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f_lza_ex4_lza_amt_cp1 :in std_ulogic_vector(0 to 7) ;
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f_lza_ex4_lza_dcd64_cp1 :in std_ulogic_vector(0 to 2);
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f_lza_ex4_lza_dcd64_cp2 :in std_ulogic_vector(0 to 1);
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f_lza_ex4_lza_dcd64_cp3 :in std_ulogic_vector(0 to 0);
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f_lza_ex4_sh_rgt_en :in std_ulogic;
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f_add_ex4_res :in std_ulogic_vector(0 to 162) ;
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f_add_ex4_sticky :in std_ulogic ;
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f_pic_ex4_byp_prod_nz :in std_ulogic ;
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f_nrm_ex5_res :out std_ulogic_vector(0 to 52) ;
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f_nrm_ex5_int_sign :out std_ulogic ;
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f_nrm_ex5_int_lsbs :out std_ulogic_vector(1 to 12) ;
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f_nrm_ex5_nrm_sticky_dp :out std_ulogic ;
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f_nrm_ex5_nrm_guard_dp :out std_ulogic ;
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f_nrm_ex5_nrm_lsb_dp :out std_ulogic ;
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f_nrm_ex5_nrm_sticky_sp :out std_ulogic ;
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f_nrm_ex5_nrm_guard_sp :out std_ulogic ;
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f_nrm_ex5_nrm_lsb_sp :out std_ulogic ;
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f_nrm_ex5_exact_zero :out std_ulogic ;
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f_nrm_ex4_extra_shift :out std_ulogic ;
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f_nrm_ex5_fpscr_wr_dat_dfp :out std_ulogic_vector(0 to 3) ;
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f_nrm_ex5_fpscr_wr_dat :out std_ulogic_vector(0 to 31)
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);
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end fuq_nrm;
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architecture fuq_nrm of fuq_nrm is
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constant tiup :std_ulogic := '1';
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constant tidn :std_ulogic := '0';
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signal sg_0 :std_ulogic ;
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signal thold_0_b, thold_0, forcee :std_ulogic ;
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signal ex3_act :std_ulogic ;
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signal ex4_act :std_ulogic ;
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signal act_spare_unused :std_ulogic_vector(0 to 2) ;
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signal act_so :std_ulogic_vector(0 to 3) ;
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signal act_si :std_ulogic_vector(0 to 3) ;
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signal ex5_res_so :std_ulogic_vector(0 to 52) ;
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signal ex5_res_si :std_ulogic_vector(0 to 52) ;
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signal ex5_nrm_lg_so :std_ulogic_vector(0 to 3) ;
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signal ex5_nrm_lg_si :std_ulogic_vector(0 to 3) ;
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signal ex5_nrm_x_so :std_ulogic_vector(0 to 2) ;
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signal ex5_nrm_x_si :std_ulogic_vector(0 to 2) ;
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signal ex5_nrm_pass_so :std_ulogic_vector(0 to 12) ;
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signal ex5_nrm_pass_si :std_ulogic_vector(0 to 12) ;
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signal ex5_fmv_so :std_ulogic_vector(0 to 35) ;
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signal ex5_fmv_si :std_ulogic_vector(0 to 35) ;
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signal ex4_sh2 :std_ulogic_vector(26 to 72) ;
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signal ex4_sh4_25 :std_ulogic ;
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signal ex4_sh4_54 :std_ulogic ;
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signal ex4_nrm_res , ex4_sh5_x_b, ex4_sh5_y_b :std_ulogic_vector(0 to 53) ;
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signal ex4_lt064_x :std_ulogic ;
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signal ex4_lt128_x :std_ulogic ;
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signal ex4_lt016_x :std_ulogic ;
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signal ex4_lt032_x :std_ulogic ;
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signal ex4_lt048_x :std_ulogic ;
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signal ex4_lt016 :std_ulogic ;
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signal ex4_lt032 :std_ulogic ;
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signal ex4_lt048 :std_ulogic ;
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signal ex4_lt064 :std_ulogic ;
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signal ex4_lt080 :std_ulogic ;
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signal ex4_lt096 :std_ulogic ;
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signal ex4_lt112 :std_ulogic ;
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signal ex4_lt128 :std_ulogic ;
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signal ex4_lt04_x :std_ulogic ;
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signal ex4_lt08_x :std_ulogic ;
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signal ex4_lt12_x :std_ulogic ;
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signal ex4_lt01_x :std_ulogic ;
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signal ex4_lt02_x :std_ulogic ;
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signal ex4_lt03_x :std_ulogic ;
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signal ex4_sticky_sp :std_ulogic ;
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signal ex4_sticky_dp :std_ulogic ;
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signal ex4_sticky16_dp :std_ulogic ;
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signal ex4_sticky16_sp :std_ulogic ;
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signal ex4_or_grp16 :std_ulogic_vector(0 to 10) ;
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signal ex4_lt :std_ulogic_vector(0 to 14) ;
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signal ex4_exact_zero :std_ulogic ;
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signal ex4_exact_zero_b :std_ulogic ;
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signal ex5_res :std_ulogic_vector(0 to 52);
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signal ex5_nrm_sticky_dp :std_ulogic;
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signal ex5_nrm_guard_dp :std_ulogic;
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signal ex5_nrm_lsb_dp :std_ulogic;
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signal ex5_nrm_sticky_sp :std_ulogic;
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signal ex5_nrm_guard_sp :std_ulogic;
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signal ex5_nrm_lsb_sp :std_ulogic;
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signal ex5_exact_zero :std_ulogic;
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signal ex5_int_sign :std_ulogic;
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signal ex5_int_lsbs :std_ulogic_vector(1 to 12);
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signal ex5_fpscr_wr_dat :std_ulogic_vector(0 to 31);
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signal ex5_fpscr_wr_dat_dfp :std_ulogic_vector(0 to 3);
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signal ex4_rgt_4more, ex4_rgt_3more, ex4_rgt_2more :std_ulogic;
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signal ex4_shift_extra_cp2 :std_ulogic;
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signal unused :std_ulogic;
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signal ex4_sticky_dp_x2_b, ex4_sticky_dp_x1_b, ex4_sticky_dp_x1 :std_ulogic;
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signal ex4_sticky_sp_x2_b, ex4_sticky_sp_x1_b, ex4_sticky_sp_x1 :std_ulogic;
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signal ex5_d1clk, ex5_d2clk :std_ulogic ;
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signal ex5_lclk :clk_logic;
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signal ex4_sticky_stuff :std_ulogic ;
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begin
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unused <= or_reduce( ex4_sh2(41 to 54) ) or
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or_reduce( ex4_nrm_res(0 to 53) ) or
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ex4_sticky_sp or
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ex4_sticky_dp or
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ex4_exact_zero ;
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thold_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => thold_1,
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q(0) => thold_0 );
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sg_reg_0: tri_plat generic map (expand_type => expand_type) port map (
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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flush => flush ,
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din(0) => sg_1 ,
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q(0) => sg_0 );
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lcbor_0: tri_lcbor generic map (expand_type => expand_type ) port map (
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clkoff_b => clkoff_b,
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thold => thold_0,
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sg => sg_0,
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act_dis => act_dis,
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forcee => forcee,
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thold_b => thold_0_b );
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ex5_lcb : tri_lcbnd generic map (expand_type => expand_type) port map(
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delay_lclkr => delay_lclkr(5) ,
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mpw1_b => mpw1_b(5) ,
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mpw2_b => mpw2_b(1) ,
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forcee => forcee,
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nclk => nclk ,
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vd => vdd ,
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gd => gnd ,
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act => ex4_act ,
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sg => sg_0 ,
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thold_b => thold_0_b ,
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d1clk => ex5_d1clk ,
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d2clk => ex5_d2clk ,
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lclk => ex5_lclk );
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ex3_act <= not ex3_act_b ;
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act_lat: tri_rlmreg_p generic map (width=> 4, expand_type => expand_type, needs_sreset => 0) port map (
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forcee => forcee,
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delay_lclkr => delay_lclkr(4) ,
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mpw1_b => mpw1_b(4) ,
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mpw2_b => mpw2_b(0) ,
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vd => vdd,
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gd => gnd,
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nclk => nclk,
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thold_b => thold_0_b,
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sg => sg_0,
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act => fpu_enable,
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scout => act_so (0 to 3),
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scin => act_si (0 to 3),
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din(0) => act_spare_unused(0),
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din(1) => act_spare_unused(1),
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din(2) => ex3_act,
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din(3) => act_spare_unused(2),
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dout(0) => act_spare_unused(0),
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dout(1) => act_spare_unused(1),
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dout(2) => ex4_act,
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dout(3) => act_spare_unused(2) );
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sh: entity work.fuq_nrm_sh(fuq_nrm_sh) generic map (expand_type => expand_type) port map(
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f_lza_ex4_sh_rgt_en => f_lza_ex4_sh_rgt_en ,
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f_lza_ex4_lza_amt_cp1(2 to 7) => f_lza_ex4_lza_amt_cp1(2 to 7) ,
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f_lza_ex4_lza_dcd64_cp1(0 to 2) => f_lza_ex4_lza_dcd64_cp1(0 to 2) ,
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f_lza_ex4_lza_dcd64_cp2(0 to 1) => f_lza_ex4_lza_dcd64_cp2(0 to 1) ,
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f_lza_ex4_lza_dcd64_cp3(0 to 0) => f_lza_ex4_lza_dcd64_cp3(0 to 0) ,
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f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) ,
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ex4_shift_extra_cp1 => f_nrm_ex4_extra_shift ,
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ex4_shift_extra_cp2 => ex4_shift_extra_cp2 ,
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ex4_sh4_25 => ex4_sh4_25 ,
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ex4_sh4_54 => ex4_sh4_54 ,
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ex4_sh2_o(26 to 72) => ex4_sh2(26 to 72) ,
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ex4_sh5_x_b(0 to 53) => ex4_sh5_x_b(0 to 53) ,
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ex4_sh5_y_b(0 to 53) => ex4_sh5_y_b(0 to 53) );
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ex4_nrm_res(0 to 53) <= not( ex4_sh5_x_b(0 to 53) and ex4_sh5_y_b(0 to 53) ) ;
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ex4_lt064_x <= not( f_lza_ex4_lza_amt_cp1(0) or f_lza_ex4_lza_amt_cp1(1) );
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ex4_lt128_x <= not( f_lza_ex4_lza_amt_cp1(0) );
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ex4_lt016_x <= not( f_lza_ex4_lza_amt_cp1(2) or f_lza_ex4_lza_amt_cp1(3) );
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ex4_lt032_x <= not( f_lza_ex4_lza_amt_cp1(2) );
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ex4_lt048_x <= not( f_lza_ex4_lza_amt_cp1(2) and f_lza_ex4_lza_amt_cp1(3) );
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ex4_lt016 <= ex4_lt064_x and ex4_lt016_x ;
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ex4_lt032 <= ex4_lt064_x and ex4_lt032_x ;
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ex4_lt048 <= ex4_lt064_x and ex4_lt048_x ;
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ex4_lt064 <= ex4_lt064_x ;
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ex4_lt080 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt016_x);
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ex4_lt096 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt032_x);
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ex4_lt112 <= ex4_lt064_x or (ex4_lt128_x and ex4_lt048_x);
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ex4_lt128 <= ex4_lt128_x ;
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ex4_rgt_2more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) or not f_lza_ex4_lza_amt_cp1(3) );
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ex4_rgt_3more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) );
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ex4_rgt_4more <= f_lza_ex4_sh_rgt_en and ( not f_lza_ex4_lza_amt_cp1(2) and not f_lza_ex4_lza_amt_cp1(3) );
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or16: entity work.fuq_nrm_or16(fuq_nrm_or16) generic map (expand_type => expand_type) port map(
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f_add_ex4_res(0 to 162) => f_add_ex4_res(0 to 162) ,
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ex4_or_grp16(0 to 10) => ex4_or_grp16(0 to 10) );
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ex4_sticky_stuff <=
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( f_pic_ex4_byp_prod_nz ) or
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( f_add_ex4_sticky ) ;
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ex4_sticky16_dp <=
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( ex4_or_grp16(1) and ex4_rgt_4more ) or
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( ex4_or_grp16(2) and ex4_rgt_3more ) or
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( ex4_or_grp16(3) and ex4_rgt_2more ) or
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( ex4_or_grp16(4) and f_lza_ex4_sh_rgt_en ) or
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( ex4_or_grp16(5) and (ex4_lt016 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(6) and (ex4_lt032 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(7) and (ex4_lt048 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(8) and (ex4_lt064 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(9) and (ex4_lt080 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(10) and (ex4_lt096 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_sh2(70) ) or
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( ex4_sh2(71) ) or
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( ex4_sh2(72) ) or
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( ex4_sticky_stuff ) ;
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ex4_sticky16_sp <=
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( ex4_or_grp16(0) and ex4_rgt_3more ) or
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( ex4_or_grp16(1) and ex4_rgt_2more ) or
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( ex4_or_grp16(2) and f_lza_ex4_sh_rgt_en ) or
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( ex4_or_grp16(3) and (ex4_lt016 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(4) and (ex4_lt032 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(5) and (ex4_lt048 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(6) and (ex4_lt064 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(7) and (ex4_lt080 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(8) and (ex4_lt096 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(9) and (ex4_lt112 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_or_grp16(10) and (ex4_lt128 or f_lza_ex4_sh_rgt_en) ) or
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( ex4_sticky_stuff ) ;
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ex4_exact_zero_b <=
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ex4_or_grp16(0) or
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ex4_or_grp16(1) or
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ex4_or_grp16(2) or
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ex4_or_grp16(3) or
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ex4_or_grp16(4) or
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ex4_or_grp16(5) or
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ex4_or_grp16(6) or
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ex4_or_grp16(7) or
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ex4_or_grp16(8) or
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ex4_or_grp16(9) or
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ex4_or_grp16(10) or
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( ex4_sticky_stuff ) ;
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ex4_exact_zero <= not ex4_exact_zero_b ;
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ex4_lt04_x <= not( f_lza_ex4_lza_amt_cp1(4) or f_lza_ex4_lza_amt_cp1(5) );
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ex4_lt08_x <= not( f_lza_ex4_lza_amt_cp1(4) );
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ex4_lt12_x <= not( f_lza_ex4_lza_amt_cp1(4) and f_lza_ex4_lza_amt_cp1(5) );
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ex4_lt01_x <= not( f_lza_ex4_lza_amt_cp1(6) or f_lza_ex4_lza_amt_cp1(7) );
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ex4_lt02_x <= not( f_lza_ex4_lza_amt_cp1(6) );
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ex4_lt03_x <= not( f_lza_ex4_lza_amt_cp1(6) and f_lza_ex4_lza_amt_cp1(7) );
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ex4_lt(0) <= ex4_lt04_x and ex4_lt01_x ;
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ex4_lt(1) <= ex4_lt04_x and ex4_lt02_x ;
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ex4_lt(2) <= ex4_lt04_x and ex4_lt03_x ;
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ex4_lt(3) <= ex4_lt04_x ;
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ex4_lt(4) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt01_x);
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ex4_lt(5) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt02_x);
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ex4_lt(6) <= ex4_lt04_x or (ex4_lt08_x and ex4_lt03_x);
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ex4_lt(7) <= (ex4_lt08_x );
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ex4_lt(8) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt01_x);
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ex4_lt(9) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt02_x);
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ex4_lt(10) <= ex4_lt08_x or (ex4_lt12_x and ex4_lt03_x);
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ex4_lt(11) <= (ex4_lt12_x );
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ex4_lt(12) <= ex4_lt12_x or ex4_lt01_x ;
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ex4_lt(13) <= ex4_lt12_x or ex4_lt02_x ;
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ex4_lt(14) <= ex4_lt12_x or ex4_lt03_x ;
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ex4_sticky_sp_x1 <=
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(ex4_lt(14) and ex4_sh2(40) ) or
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(ex4_lt(13) and ex4_sh2(39) ) or
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(ex4_lt(12) and ex4_sh2(38) ) or
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(ex4_lt(11) and ex4_sh2(37) ) or
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(ex4_lt(10) and ex4_sh2(36) ) or
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(ex4_lt(9) and ex4_sh2(35) ) or
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(ex4_lt(8) and ex4_sh2(34) ) or
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(ex4_lt(7) and ex4_sh2(33) ) or
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(ex4_lt(6) and ex4_sh2(32) ) or
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(ex4_lt(5) and ex4_sh2(31) ) or
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(ex4_lt(4) and ex4_sh2(30) ) or
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(ex4_lt(3) and ex4_sh2(29) ) or
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(ex4_lt(2) and ex4_sh2(28) ) or
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(ex4_lt(1) and ex4_sh2(27) ) or
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(ex4_lt(0) and ex4_sh2(26) ) or
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(ex4_sticky16_sp ) ;
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ex4_sticky_sp_x2_b <= not(not ex4_shift_extra_cp2 and ex4_sh4_25 );
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ex4_sticky_sp_x1_b <= not ex4_sticky_sp_x1 ;
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ex4_sticky_sp <= not( ex4_sticky_sp_x1_b and ex4_sticky_sp_x2_b );
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ex4_sticky_dp_x1 <=
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(ex4_lt(14) and ex4_sh2(69) ) or
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(ex4_lt(13) and ex4_sh2(68) ) or
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(ex4_lt(12) and ex4_sh2(67) ) or
|
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(ex4_lt(11) and ex4_sh2(66) ) or
|
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(ex4_lt(10) and ex4_sh2(65) ) or
|
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(ex4_lt(9) and ex4_sh2(64) ) or
|
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(ex4_lt(8) and ex4_sh2(63) ) or
|
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(ex4_lt(7) and ex4_sh2(62) ) or
|
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(ex4_lt(6) and ex4_sh2(61) ) or
|
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(ex4_lt(5) and ex4_sh2(60) ) or
|
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(ex4_lt(4) and ex4_sh2(59) ) or
|
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(ex4_lt(3) and ex4_sh2(58) ) or
|
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(ex4_lt(2) and ex4_sh2(57) ) or
|
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(ex4_lt(1) and ex4_sh2(56) ) or
|
|
(ex4_lt(0) and ex4_sh2(55) ) or
|
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(ex4_sticky16_dp ) ;
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ex4_sticky_dp_x2_b <= not(not ex4_shift_extra_cp2 and ex4_sh4_54 ) ;
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ex4_sticky_dp_x1_b <= not ex4_sticky_dp_x1 ;
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|
ex4_sticky_dp <= not( ex4_sticky_dp_x1_b and ex4_sticky_dp_x2_b );
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ex5_res_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 53, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0) port map (
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vd => vdd,
|
|
gd => gnd,
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LCLK => ex5_lclk ,
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|
D1CLK => ex5_d1clk ,
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|
D2CLK => ex5_d2clk ,
|
|
SCANIN => ex5_res_si ,
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|
SCANOUT => ex5_res_so ,
|
|
A1 => ex4_sh5_x_b(0 to 52) ,
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|
A2 => ex4_sh5_y_b(0 to 52) ,
|
|
QB => ex5_res(0 to 52) );
|
|
|
|
ex5_nrm_lg_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 4, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map (
|
|
vd => vdd,
|
|
gd => gnd,
|
|
LCLK => ex5_lclk ,
|
|
D1CLK => ex5_d1clk ,
|
|
D2CLK => ex5_d2clk ,
|
|
SCANIN => ex5_nrm_lg_si ,
|
|
SCANOUT => ex5_nrm_lg_so ,
|
|
A1(0) => ex4_sh5_x_b(23) ,
|
|
A1(1) => ex4_sh5_x_b(24) ,
|
|
A1(2) => ex4_sh5_x_b(52) ,
|
|
A1(3) => ex4_sh5_x_b(53) ,
|
|
A2(0) => ex4_sh5_y_b(23) ,
|
|
A2(1) => ex4_sh5_y_b(24) ,
|
|
A2(2) => ex4_sh5_y_b(52) ,
|
|
A2(3) => ex4_sh5_y_b(53) ,
|
|
QB(0) => ex5_nrm_lsb_sp ,
|
|
QB(1) => ex5_nrm_guard_sp ,
|
|
QB(2) => ex5_nrm_lsb_dp ,
|
|
QB(3) => ex5_nrm_guard_dp );
|
|
|
|
|
|
|
|
|
|
|
|
ex5_nrm_x_lat: entity tri.tri_nand2_nlats(tri_nand2_nlats) generic map (width=> 3, btr => "NLA0001_X1_A12TH", expand_type => expand_type, needs_sreset => 0 ) port map (
|
|
vd => vdd,
|
|
gd => gnd,
|
|
LCLK => ex5_lclk ,
|
|
D1CLK => ex5_d1clk ,
|
|
D2CLK => ex5_d2clk ,
|
|
SCANIN => ex5_nrm_x_si ,
|
|
SCANOUT => ex5_nrm_x_so ,
|
|
A1(0) => ex4_sticky_sp_x2_b ,
|
|
A1(1) => ex4_sticky_dp_x2_b ,
|
|
A1(2) => ex4_exact_zero_b ,
|
|
A2(0) => ex4_sticky_sp_x1_b ,
|
|
A2(1) => ex4_sticky_dp_x1_b ,
|
|
A2(2) => tiup ,
|
|
QB(0) => ex5_nrm_sticky_sp ,
|
|
QB(1) => ex5_nrm_sticky_dp ,
|
|
QB(2) => ex5_exact_zero );
|
|
|
|
ex5_nrm_pass_lat: tri_rlmreg_p generic map (width=> 13, expand_type => expand_type, ibuf => true, needs_sreset => 0) port map (
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr(5) ,
|
|
mpw1_b => mpw1_b(5) ,
|
|
mpw2_b => mpw2_b(1) ,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
thold_b => thold_0_b,
|
|
sg => sg_0,
|
|
act => ex4_act,
|
|
scout => ex5_nrm_pass_so,
|
|
scin => ex5_nrm_pass_si,
|
|
din(0) => f_add_ex4_res(99) ,
|
|
din(1 to 12) => f_add_ex4_res(151 to 162) ,
|
|
dout(0) => ex5_int_sign ,
|
|
dout(1 to 12) => ex5_int_lsbs (1 to 12) );
|
|
|
|
ex5_fmv_lat: tri_rlmreg_p generic map (width=> 36, expand_type => expand_type, ibuf => true, needs_sreset => 1) port map (
|
|
forcee => forcee,
|
|
delay_lclkr => delay_lclkr(5) ,
|
|
mpw1_b => mpw1_b(5) ,
|
|
mpw2_b => mpw2_b(1) ,
|
|
vd => vdd,
|
|
gd => gnd,
|
|
nclk => nclk,
|
|
thold_b => thold_0_b,
|
|
sg => sg_0,
|
|
act => ex4_act,
|
|
scout => ex5_fmv_so ,
|
|
scin => ex5_fmv_si ,
|
|
din => f_add_ex4_res(17 to 52) ,
|
|
dout(0 to 3) => ex5_fpscr_wr_dat_dfp(0 to 3) ,
|
|
dout(4 to 35) => ex5_fpscr_wr_dat(0 to 31) );
|
|
|
|
|
|
|
|
f_nrm_ex5_res <= ex5_res(0 to 52) ;
|
|
f_nrm_ex5_nrm_lsb_sp <= ex5_nrm_lsb_sp ;
|
|
f_nrm_ex5_nrm_guard_sp <= ex5_nrm_guard_sp ;
|
|
f_nrm_ex5_nrm_sticky_sp <= ex5_nrm_sticky_sp ;
|
|
f_nrm_ex5_nrm_lsb_dp <= ex5_nrm_lsb_dp ;
|
|
f_nrm_ex5_nrm_guard_dp <= ex5_nrm_guard_dp ;
|
|
f_nrm_ex5_nrm_sticky_dp <= ex5_nrm_sticky_dp ;
|
|
f_nrm_ex5_exact_zero <= ex5_exact_zero ;
|
|
f_nrm_ex5_int_lsbs <= ex5_int_lsbs (1 to 12) ;
|
|
f_nrm_ex5_fpscr_wr_dat <= ex5_fpscr_wr_dat(0 to 31) ;
|
|
f_nrm_ex5_fpscr_wr_dat_dfp <= ex5_fpscr_wr_dat_dfp(0 to 3) ;
|
|
f_nrm_ex5_int_sign <= ex5_int_sign ;
|
|
|
|
|
|
|
|
act_si (0 to 3) <= act_so (1 to 3) & f_nrm_si;
|
|
ex5_res_si (0 to 52) <= ex5_res_so (1 to 52) & act_so(0) ;
|
|
ex5_nrm_lg_si(0 to 3) <= ex5_nrm_lg_so(1 to 3) & ex5_res_so(0);
|
|
ex5_nrm_x_si(0 to 2) <= ex5_nrm_x_so(1 to 2) & ex5_nrm_lg_so(0);
|
|
ex5_nrm_pass_si(0 to 12) <= ex5_nrm_pass_so(1 to 12) & ex5_nrm_x_so(0);
|
|
ex5_fmv_si (0 to 35) <= ex5_fmv_so (1 to 35) & ex5_nrm_pass_so(0);
|
|
f_nrm_so <= ex5_fmv_so (0) ;
|
|
|
|
|
|
|
|
end;
|
|
|
|
|
|
|
|
|