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234 lines
9.8 KiB
VHDL
234 lines
9.8 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all ;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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ENTITY fuq_tblmul_bthrow IS
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PORT(
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x :in std_ulogic_vector(0 to 15);
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s_neg :in std_ulogic;
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s_x :in std_ulogic;
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s_x2 :in std_ulogic;
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q :out std_ulogic_vector(0 to 16)
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);
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end fuq_tblmul_bthrow;
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architecture fuq_tblmul_bthrow of fuq_tblmul_bthrow is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal left :std_ulogic_vector( 0 to 16);
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signal unused :std_ulogic;
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begin
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unused <= left(0);
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u00: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => tidn ,
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LEFT => left(0) ,
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RIGHT => left(1) ,
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Q => q(0) );
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u01: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(0) ,
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LEFT => left(1) ,
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RIGHT => left(2) ,
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Q => q(1) );
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u02: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(1) ,
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LEFT => left(2) ,
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RIGHT => left(3) ,
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Q => q(2) );
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u03: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(2) ,
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LEFT => left(3) ,
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RIGHT => left(4) ,
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Q => q(3) );
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u04: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(3) ,
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LEFT => left(4) ,
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RIGHT => left(5) ,
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Q => q(4) );
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u05: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(4) ,
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LEFT => left(5) ,
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RIGHT => left(6) ,
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Q => q(5) );
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u06: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(5) ,
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LEFT => left(6) ,
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RIGHT => left(7) ,
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Q => q(6) );
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u07: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(6) ,
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LEFT => left(7) ,
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RIGHT => left(8) ,
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Q => q(7) );
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u08: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(7) ,
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LEFT => left(8) ,
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RIGHT => left(9) ,
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Q => q(8) );
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u09: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(8) ,
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LEFT => left(9) ,
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RIGHT => left(10) ,
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Q => q(9) );
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u10: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(9) ,
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LEFT => left(10) ,
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RIGHT => left(11) ,
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Q => q(10) );
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u11: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(10) ,
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LEFT => left(11) ,
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RIGHT => left(12) ,
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Q => q(11) );
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u12: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(11) ,
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LEFT => left(12) ,
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RIGHT => left(13) ,
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Q => q(12) );
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u13: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(12) ,
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LEFT => left(13) ,
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RIGHT => left(14) ,
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Q => q(13) );
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u14: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(13) ,
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LEFT => left(14) ,
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RIGHT => left(15) ,
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Q => q(14) );
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u15: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(14) ,
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LEFT => left(15) ,
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RIGHT => left(16) ,
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Q => q(15) );
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u16: entity work.fuq_mul_bthmux(fuq_mul_bthmux) port map(
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SNEG => s_neg ,
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SX => s_x ,
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SX2 => s_x2 ,
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X => x(15) ,
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LEFT => left(16) ,
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RIGHT => s_neg ,
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Q => q(16) );
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end;
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