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268 lines
9.3 KiB
VHDL
268 lines
9.3 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee,ibm,support,tri,work;
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use ieee.std_logic_1164.all;
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use ibm.std_ulogic_unsigned.all;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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use tri.tri_latches_pkg.all;
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use ibm.std_ulogic_ao_support.all;
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use ibm.std_ulogic_mux_support.all;
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entity xuq_add is
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generic( expand_type : integer := 2 );
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port(
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x_b :in std_ulogic_vector(0 to 63) ;
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y_b :in std_ulogic_vector(0 to 63) ;
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ci :in std_ulogic_vector(8 to 8) ;
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sum :out std_ulogic_vector(0 to 63);
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cout_32 :out std_ulogic ;
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cout_0 :out std_ulogic
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);
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end xuq_add;
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architecture xuq_add of xuq_add is
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constant tiup : std_ulogic := '1';
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constant tidn : std_ulogic := '0';
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signal g01, g01_b :std_ulogic_vector(0 to 63);
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signal t01, t01_b :std_ulogic_vector(0 to 63);
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signal sum_0, sum_1 :std_ulogic_vector(0 to 63);
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signal g08 :std_ulogic_vector(0 to 7);
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signal t08 :std_ulogic_vector(0 to 7);
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signal c64_b :std_ulogic_vector(0 to 7);
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signal cout_32x , cout_32y_b :std_ulogic;
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signal ci_cp1_lv1_b , ci_cp1_lv2 , ci_cp1_lv3_b , ci_cp1_lv4 :std_ulogic;
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signal ci_cp2_lv2 , ci_cp2_lv3_b :std_ulogic;
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begin
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u_ci_11: ci_cp1_lv1_b <= not ci(8) ;
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u_ci_12: ci_cp1_lv2 <= not ci_cp1_lv1_b ;
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u_ci_13: ci_cp1_lv3_b <= not ci_cp1_lv2 ;
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u_ci_14: ci_cp1_lv4 <= not ci_cp1_lv3_b ;
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u_ci_22: ci_cp2_lv2 <= not ci_cp1_lv1_b ;
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u_ci_23: ci_cp2_lv3_b <= not ci_cp2_lv2 ;
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u_g01: g01(0 to 63) <= not( x_b(0 to 63) or y_b(0 to 63) );
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u_t01: t01(0 to 63) <= not( x_b(0 to 63) and y_b(0 to 63) );
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u_g01b: g01_b(0 to 63) <= not g01(0 to 63);
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u_t01b: t01_b(0 to 63) <= not t01(0 to 63);
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loc_0: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(0 to 7) ,
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t01_b(0 to 7) => t01_b(0 to 7) ,
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sum_0(0 to 7) => sum_0(0 to 7) ,
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sum_1(0 to 7) => sum_1(0 to 7) );
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loc_1: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(8 to 15) ,
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t01_b(0 to 7) => t01_b(8 to 15) ,
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sum_0(0 to 7) => sum_0(8 to 15) ,
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sum_1(0 to 7) => sum_1(8 to 15) );
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loc_2: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(16 to 23) ,
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t01_b(0 to 7) => t01_b(16 to 23) ,
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sum_0(0 to 7) => sum_0(16 to 23) ,
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sum_1(0 to 7) => sum_1(16 to 23) );
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loc_3: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(24 to 31) ,
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t01_b(0 to 7) => t01_b(24 to 31) ,
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sum_0(0 to 7) => sum_0(24 to 31) ,
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sum_1(0 to 7) => sum_1(24 to 31) );
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loc_4: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(32 to 39) ,
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t01_b(0 to 7) => t01_b(32 to 39) ,
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sum_0(0 to 7) => sum_0(32 to 39) ,
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sum_1(0 to 7) => sum_1(32 to 39) );
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loc_5: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(40 to 47) ,
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t01_b(0 to 7) => t01_b(40 to 47) ,
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sum_0(0 to 7) => sum_0(40 to 47) ,
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sum_1(0 to 7) => sum_1(40 to 47) );
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loc_6: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(48 to 55) ,
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t01_b(0 to 7) => t01_b(48 to 55) ,
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sum_0(0 to 7) => sum_0(48 to 55) ,
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sum_1(0 to 7) => sum_1(48 to 55) );
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loc_7: entity work.xuq_add_loc(xuq_add_loc) port map(
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g01_b(0 to 7) => g01_b(56 to 63) ,
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t01_b(0 to 7) => t01_b(56 to 63) ,
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sum_0(0 to 7) => sum_0(56 to 63) ,
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sum_1(0 to 7) => sum_1(56 to 63) );
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gclc_0: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(0 to 7) ,
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t01(0 to 7) => t01(0 to 7) ,
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g08 => g08(0) ,
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t08 => t08(0) );
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gclc_1: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(8 to 15) ,
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t01(0 to 7) => t01(8 to 15) ,
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g08 => g08(1) ,
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t08 => t08(1) );
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gclc_2: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(16 to 23) ,
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t01(0 to 7) => t01(16 to 23) ,
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g08 => g08(2) ,
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t08 => t08(2) );
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gclc_3: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(24 to 31) ,
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t01(0 to 7) => t01(24 to 31) ,
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g08 => g08(3) ,
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t08 => t08(3) );
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gclc_4: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(32 to 39) ,
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t01(0 to 7) => t01(32 to 39) ,
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g08 => g08(4) ,
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t08 => t08(4) );
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gclc_5: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(40 to 47) ,
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t01(0 to 7) => t01(40 to 47) ,
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g08 => g08(5) ,
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t08 => t08(5) );
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gclc_6: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(48 to 55) ,
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t01(0 to 7) => t01(48 to 55) ,
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g08 => g08(6) ,
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t08 => t08(6) );
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gclc_7: entity work.xuq_add_glbloc(xuq_add_glbloc) port map(
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g01(0 to 7) => g01(56 to 63) ,
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t01(0 to 7) => t01(56 to 63) ,
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g08 => g08(7) ,
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t08 => t08(7) );
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gc: entity work.xuq_add_glbglbci(xuq_add_glbglbci) port map(
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g08(0 to 7) => g08(0 to 7) ,
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t08(0 to 7) => t08(0 to 7) ,
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ci => ci_cp1_lv4 ,
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c64_b(0 to 7) => c64_b(0 to 7) );
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u_c32x: cout_32x <= not c64_b(4) ;
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u_c32y: cout_32y_b <= not cout_32x ;
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u_c32: cout_32 <= not cout_32y_b ;
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u_c64: cout_0 <= not c64_b(0) ;
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fm_0: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => c64_b(1) ,
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sum_0(0 to 7) => sum_0(0 to 7) ,
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sum_1(0 to 7) => sum_1(0 to 7) ,
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sum (0 to 7) => sum (0 to 7) );
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fm_1: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => c64_b(2) ,
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sum_0(0 to 7) => sum_0(8 to 15) ,
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sum_1(0 to 7) => sum_1(8 to 15) ,
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sum (0 to 7) => sum (8 to 15) );
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fm_2: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => c64_b(3) ,
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sum_0(0 to 7) => sum_0(16 to 23) ,
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sum_1(0 to 7) => sum_1(16 to 23) ,
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sum (0 to 7) => sum (16 to 23) );
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fm_3: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => c64_b(4) ,
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sum_0(0 to 7) => sum_0(24 to 31) ,
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sum_1(0 to 7) => sum_1(24 to 31) ,
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sum (0 to 7) => sum (24 to 31) );
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fm_4: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => c64_b(5) ,
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sum_0(0 to 7) => sum_0(32 to 39) ,
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sum_1(0 to 7) => sum_1(32 to 39) ,
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sum (0 to 7) => sum (32 to 39) );
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fm_5: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => c64_b(6) ,
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sum_0(0 to 7) => sum_0(40 to 47) ,
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sum_1(0 to 7) => sum_1(40 to 47) ,
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sum (0 to 7) => sum (40 to 47) );
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fm_6: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => c64_b(7) ,
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sum_0(0 to 7) => sum_0(48 to 55) ,
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sum_1(0 to 7) => sum_1(48 to 55) ,
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sum (0 to 7) => sum (48 to 55) );
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fm_7: entity work.xuq_add_csmux(xuq_add_csmux) port map(
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ci_b => ci_cp2_lv3_b ,
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sum_0(0 to 7) => sum_0(56 to 63) ,
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sum_1(0 to 7) => sum_1(56 to 63) ,
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sum (0 to 7) => sum (56 to 63) );
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end;
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