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385 lines
22 KiB
VHDL
385 lines
22 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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library UNIMACRO;
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use UNIMACRO.vcomponents.all;
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entity RAMB16_S9_S9 is
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generic (
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INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_A : bit_vector := X"000000000";
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INIT_B : bit_vector := X"000000000";
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SIM_COLLISION_CHECK : string := "ALL";
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SRVAL_A : bit_vector := X"000000000";
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SRVAL_B : bit_vector := X"000000000";
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WRITE_MODE_A : string := "WRITE_FIRST";
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WRITE_MODE_B : string := "WRITE_FIRST"
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);
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port (
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DOA : out std_logic_vector(7 downto 0);
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DOB : out std_logic_vector(7 downto 0);
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DOPA : out std_logic_vector(0 downto 0);
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DOPB : out std_logic_vector(0 downto 0);
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ADDRA : in std_logic_vector(10 downto 0);
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ADDRB : in std_logic_vector(10 downto 0);
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector(7 downto 0);
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DIB : in std_logic_vector(7 downto 0);
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DIPA : in std_logic_vector(0 downto 0);
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DIPB : in std_logic_vector(0 downto 0);
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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SSRA : in std_ulogic;
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SSRB : in std_ulogic;
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WEA : in std_ulogic;
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WEB : in std_ulogic
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);
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end RAMB16_S9_S9;
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architecture RAMB16_S9_S9 of RAMB16_S9_S9 is
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signal DINA, DINB : std_logic_vector(8 downto 0);
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signal DOUTA, DOUTB : std_logic_vector(8 downto 0);
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signal SSRA_t, SSRB_t : std_logic;
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signal WEA_t, WEB_t : std_logic_vector(0 downto 0);
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begin
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DINA <= DIPA & DIA;
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DOPA(0) <= DOUTA(8);
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DOA <= DOUTA(7 downto 0);
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DINB <= DIPB & DIB;
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DOPB(0) <= DOUTB(8);
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DOB <= DOUTB(7 downto 0);
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SSRA_t <= SSRA;
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SSRB_t <= SSRB;
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WEA_t(0) <= WEA;
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WEB_t(0) <= WEB;
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-- BRAM_TDP_MACRO: True Dual Port RAM
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-- Virtex-7
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-- Xilinx HDL Language Template, version 2019.1
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-- Note - This Unimacro model assumes the port directions to be "downto".
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-- Simulation of this model with "to" in the port directions could lead to erroneous results.
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--------------------------------------------------------------------------
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-- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width --
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-- ===============|===========|===========|===============|=============--
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-- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit --
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-- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit --
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-- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit --
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-- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit --
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-- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit -- * using
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-- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit --
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-- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit --
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-- 2 | "36Kb" | 16384 | 14-bit | 1-bit --
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-- 2 | "18Kb" | 8192 | 13-bit | 1-bit --
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-- 1 | "36Kb" | 32768 | 15-bit | 1-bit --
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-- 1 | "18Kb" | 16384 | 14-bit | 1-bit --
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--------------------------------------------------------------------------
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BRAM_0 : BRAM_TDP_MACRO
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generic map (
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BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
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DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
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DOA_REG => 0, -- Optional port A output register (0 or 1)
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DOB_REG => 0, -- Optional port B output register (0 or 1)
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INIT_A => INIT_A, -- Initial values on A output port
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INIT_B => INIT_B, -- Initial values on B output port
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INIT_FILE => "NONE",
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READ_WIDTH_A => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
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READ_WIDTH_B => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
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SIM_COLLISION_CHECK => "NONE",
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SRVAL_A => SRVAL_A, -- Set/Reset value for A port output
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SRVAL_B => SRVAL_A, -- Set/Reset value for B port output
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WRITE_MODE_A => WRITE_MODE_A, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
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WRITE_MODE_B => WRITE_MODE_B, -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
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WRITE_WIDTH_A => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
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WRITE_WIDTH_B => 9, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
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-- The following INIT_xx declarations specify the initial contents of the RAM
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INIT_00 => INIT_00,
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INIT_01 => INIT_01,
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INIT_02 => INIT_02,
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INIT_03 => INIT_03,
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INIT_04 => INIT_04,
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INIT_05 => INIT_05,
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INIT_06 => INIT_06,
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INIT_07 => INIT_07,
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INIT_08 => INIT_08,
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INIT_09 => INIT_09,
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INIT_0A => INIT_0A,
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INIT_0B => INIT_0B,
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INIT_0C => INIT_0C,
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INIT_0D => INIT_0D,
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INIT_0E => INIT_0E,
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INIT_0F => INIT_0F,
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INIT_10 => INIT_10,
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INIT_11 => INIT_11,
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INIT_12 => INIT_12,
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INIT_13 => INIT_13,
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INIT_14 => INIT_14,
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INIT_15 => INIT_15,
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INIT_16 => INIT_16,
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INIT_17 => INIT_17,
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INIT_18 => INIT_18,
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INIT_19 => INIT_19,
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INIT_1A => INIT_1A,
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INIT_1B => INIT_1B,
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INIT_1C => INIT_1C,
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INIT_1D => INIT_1D,
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INIT_1E => INIT_1E,
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INIT_1F => INIT_1F,
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INIT_20 => INIT_20,
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INIT_21 => INIT_21,
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INIT_22 => INIT_22,
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INIT_23 => INIT_23,
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INIT_24 => INIT_24,
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INIT_25 => INIT_25,
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INIT_26 => INIT_26,
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INIT_27 => INIT_27,
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INIT_28 => INIT_28,
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INIT_29 => INIT_29,
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INIT_2A => INIT_2A,
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INIT_2B => INIT_2B,
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INIT_2C => INIT_2C,
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INIT_2D => INIT_2D,
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INIT_2E => INIT_2E,
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INIT_2F => INIT_2F,
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INIT_30 => INIT_30,
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INIT_31 => INIT_31,
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INIT_32 => INIT_32,
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INIT_33 => INIT_33,
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INIT_34 => INIT_34,
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INIT_35 => INIT_35,
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INIT_36 => INIT_36,
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INIT_37 => INIT_37,
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INIT_38 => INIT_38,
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INIT_39 => INIT_39,
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INIT_3A => INIT_3A,
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INIT_3B => INIT_3B,
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INIT_3C => INIT_3C,
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INIT_3D => INIT_3D,
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INIT_3E => INIT_3E,
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INIT_3F => INIT_3F,
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-- The next set of INIT_xx are valid when configured as 36Kb
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INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
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-- The next set of INITP_xx are for the parity bits
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INITP_00 => INITP_00,
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INITP_01 => INITP_01,
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INITP_02 => INITP_02,
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INITP_03 => INITP_03,
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INITP_04 => INITP_04,
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INITP_05 => INITP_05,
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INITP_06 => INITP_06,
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INITP_07 => INITP_07,
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-- The next set of INIT_xx are valid when configured as 36Kb
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INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
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)
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port map (
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DOA => DOUTA, -- Output port-A data, width defined by READ_WIDTH_A parameter
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DOB => DOUTB, -- Output port-B data, width defined by READ_WIDTH_B parameter
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ADDRA => ADDRA, -- Input port-A address, width defined by Port A depth
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ADDRB => ADDRB, -- Input port-B address, width defined by Port B depth
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CLKA => CLKA, -- 1-bit input port-A clock
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CLKB => CLKB, -- 1-bit input port-B clock
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DIA => DINA, -- Input port-A data, width defined by WRITE_WIDTH_A parameter
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DIB => DINB, -- Input port-B data, width defined by WRITE_WIDTH_B parameter
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ENA => ENA, -- 1-bit input port-A enable
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ENB => ENB, -- 1-bit input port-B enable
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REGCEA => '1', -- REGCEA, -- 1-bit input port-A output register enable
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REGCEB => '1', -- REGCEB, -- 1-bit input port-B output register enable
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RSTA => SSRA_t, -- 1-bit input port-A reset
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RSTB => SSRB_t, -- 1-bit input port-B reset
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WEA => WEA_t, -- Input port-A write enable, width defined by Port A depth
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WEB => WEB_t -- Input port-B write enable, width defined by Port B depth
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);
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-- End of BRAM_TDP_MACRO_inst instantiation
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end RAMB16_S9_S9;
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