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460 lines
20 KiB
VHDL
460 lines
20 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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--********************************************************************
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--*
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--* TITLE: D-ERAT CAM Match Line Logic for Functional Model
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--*
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--* NAME: tri_cam_32x143_1r1w1c_matchline
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--*
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library ieee;
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use ieee.std_logic_1164.all ;
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library ibm;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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------------------------------------------------------------------------
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-- Entity
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------------------------------------------------------------------------
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entity tri_cam_32x143_1r1w1c_matchline is
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generic (have_xbit : integer := 1;
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num_pgsizes : integer := 5;
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have_cmpmask : integer := 1;
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cmpmask_width : integer := 4);
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port( -- @{default:nclk}@
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addr_in : in std_ulogic_vector(0 to 51);
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addr_enable : in std_ulogic_vector(0 to 1);
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comp_pgsize : in std_ulogic_vector(0 to 2);
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pgsize_enable : in std_ulogic;
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entry_size : in std_ulogic_vector(0 to 2);
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entry_cmpmask : in std_ulogic_vector(0 to cmpmask_width-1);
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entry_xbit : in std_ulogic;
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entry_xbitmask : in std_ulogic_vector(0 to cmpmask_width-1);
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entry_epn : in std_ulogic_vector(0 to 51);
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comp_class : in std_ulogic_vector(0 to 1);
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entry_class : in std_ulogic_vector(0 to 1);
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class_enable : in std_ulogic_vector(0 to 2);
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comp_extclass : in std_ulogic_vector(0 to 1);
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entry_extclass : in std_ulogic_vector(0 to 1);
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extclass_enable : in std_ulogic_vector(0 to 1);
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comp_state : in std_ulogic_vector(0 to 1);
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entry_hv : in std_ulogic;
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entry_ds : in std_ulogic;
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state_enable : in std_ulogic_vector(0 to 1);
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entry_thdid : in std_ulogic_vector(0 to 3);
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comp_thdid : in std_ulogic_vector(0 to 3);
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thdid_enable : in std_ulogic_vector(0 to 1);
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entry_pid : in std_ulogic_vector(0 to 7);
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comp_pid : in std_ulogic_vector(0 to 7);
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pid_enable : in std_ulogic;
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entry_v : in std_ulogic;
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comp_invalidate : in std_ulogic;
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match : out std_ulogic
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end tri_cam_32x143_1r1w1c_matchline;
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architecture tri_cam_32x143_1r1w1c_matchline of tri_cam_32x143_1r1w1c_matchline is
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------------------------------------------------------------------------
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-- Signals
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------------------------------------------------------------------------
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signal entry_epn_b : std_ulogic_vector(34 to 51);
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signal function_50_51 : std_ulogic;
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signal function_48_51 : std_ulogic;
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signal function_46_51 : std_ulogic;
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signal function_44_51 : std_ulogic;
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signal function_40_51 : std_ulogic;
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signal function_36_51 : std_ulogic;
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signal function_34_51 : std_ulogic;
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signal pgsize_eq_16K : std_ulogic;
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signal pgsize_eq_64K : std_ulogic;
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signal pgsize_eq_256K : std_ulogic;
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signal pgsize_eq_1M : std_ulogic;
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signal pgsize_eq_16M : std_ulogic;
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signal pgsize_eq_256M : std_ulogic;
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signal pgsize_eq_1G : std_ulogic;
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signal pgsize_gte_16K : std_ulogic;
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signal pgsize_gte_64K : std_ulogic;
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signal pgsize_gte_256K : std_ulogic;
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signal pgsize_gte_1M : std_ulogic;
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signal pgsize_gte_16M : std_ulogic;
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signal pgsize_gte_256M : std_ulogic;
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signal pgsize_gte_1G : std_ulogic;
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signal comp_or_34_35 : std_ulogic;
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signal comp_or_34_39 : std_ulogic;
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signal comp_or_36_39 : std_ulogic;
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signal comp_or_40_43 : std_ulogic;
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signal comp_or_44_45 : std_ulogic;
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signal comp_or_44_47 : std_ulogic;
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signal comp_or_46_47 : std_ulogic;
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signal comp_or_48_49 : std_ulogic;
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signal comp_or_48_51 : std_ulogic;
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signal comp_or_50_51 : std_ulogic;
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signal match_line : std_ulogic_vector(0 to 72);
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signal pgsize_match : std_ulogic;
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signal addr_match : std_ulogic;
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signal class_match : std_ulogic;
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signal extclass_match : std_ulogic;
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signal state_match : std_ulogic;
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signal thdid_match : std_ulogic;
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signal pid_match : std_ulogic;
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begin
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match_line(0 to 72) <= not((entry_epn(0 to 51) & entry_size(0 to 2) & entry_class(0 to 1) & entry_extclass(0 to 1) & entry_hv & entry_ds & entry_pid(0 to 7) & entry_thdid(0 to 3)) xor
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(addr_in(0 to 51) & comp_pgsize(0 to 2) & comp_class(0 to 1) & comp_extclass(0 to 1) & comp_state(0 to 1) & comp_pid(0 to 7) & comp_thdid(0 to 3))
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);
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numpgsz8 : if num_pgsizes = 8 generate
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entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
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gen_nocmpmask80 : if have_cmpmask = 0 generate
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pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) );
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pgsize_eq_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2)));
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pgsize_eq_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) );
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pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2)));
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pgsize_eq_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) );
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pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2)));
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pgsize_eq_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) );
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pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and entry_size(2) );
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pgsize_gte_256M <= ( entry_size(0) and entry_size(1) and not(entry_size(2))) or
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pgsize_gte_1G;
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pgsize_gte_16M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2) ) or
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pgsize_gte_256M;
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pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and not(entry_size(2))) or
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pgsize_gte_16M;
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pgsize_gte_256K <= (not(entry_size(0)) and entry_size(1) and entry_size(2) ) or
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pgsize_gte_1M;
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pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and not(entry_size(2))) or
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pgsize_gte_256K;
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pgsize_gte_16K <= (not(entry_size(0)) and not(entry_size(1)) and entry_size(2) ) or
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pgsize_gte_64K;
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end generate gen_nocmpmask80;
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gen_cmpmask80 : if have_cmpmask = 1 generate
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-- size entry_cmpmask: 0123456
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-- 1GB 0000000
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-- 256MB 1000000
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-- 16MB 1100000
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-- 1MB 1110000
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-- 256KB 1111000
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-- 64KB 1111100
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-- 16KB 1111110
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-- 4KB 1111111
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pgsize_gte_1G <= not entry_cmpmask(0);
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pgsize_gte_256M <= not entry_cmpmask(1);
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pgsize_gte_16M <= not entry_cmpmask(2);
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pgsize_gte_1M <= not entry_cmpmask(3);
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pgsize_gte_256K <= not entry_cmpmask(4);
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pgsize_gte_64K <= not entry_cmpmask(5);
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pgsize_gte_16K <= not entry_cmpmask(6);
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-- size entry_xbitmask: 0123456
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-- 1GB 1000000
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-- 256MB 0100000
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-- 16MB 0010000
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-- 1MB 0001000
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-- 256KB 0000100
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-- 64KB 0000010
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-- 16KB 0000001
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-- 4KB 0000000
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pgsize_eq_1G <= entry_xbitmask(0);
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pgsize_eq_256M <= entry_xbitmask(1);
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pgsize_eq_16M <= entry_xbitmask(2);
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pgsize_eq_1M <= entry_xbitmask(3);
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pgsize_eq_256K <= entry_xbitmask(4);
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pgsize_eq_64K <= entry_xbitmask(5);
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pgsize_eq_16K <= entry_xbitmask(6);
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end generate gen_cmpmask80;
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gen_noxbit80 : if have_xbit = 0 generate
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function_34_51 <= '0';
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function_36_51 <= '0';
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function_40_51 <= '0';
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function_44_51 <= '0';
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function_46_51 <= '0';
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function_48_51 <= '0';
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function_50_51 <= '0';
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end generate gen_noxbit80;
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gen_xbit80 : if have_xbit /= 0 generate
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function_34_51 <= not(entry_xbit) or
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not(pgsize_eq_1G) or
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or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
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function_36_51 <= not(entry_xbit) or
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not(pgsize_eq_256M) or
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or_reduce(entry_epn_b(36 to 51) and addr_in(36 to 51));
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function_40_51 <= not(entry_xbit) or
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not(pgsize_eq_16M) or
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or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
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function_44_51 <= not(entry_xbit) or
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not(pgsize_eq_1M) or
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or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
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function_46_51 <= not(entry_xbit) or
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not(pgsize_eq_256K) or
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or_reduce(entry_epn_b(46 to 51) and addr_in(46 to 51));
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function_48_51 <= not(entry_xbit) or
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not(pgsize_eq_64K) or
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or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
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function_50_51 <= not(entry_xbit) or
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not(pgsize_eq_16K) or
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or_reduce(entry_epn_b(50 to 51) and addr_in(50 to 51));
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end generate gen_xbit80;
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comp_or_50_51 <= and_reduce(match_line(50 to 51)) or pgsize_gte_16K;
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comp_or_48_49 <= and_reduce(match_line(48 to 49)) or pgsize_gte_64K;
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comp_or_46_47 <= and_reduce(match_line(46 to 47)) or pgsize_gte_256K;
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comp_or_44_45 <= and_reduce(match_line(44 to 45)) or pgsize_gte_1M;
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comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
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comp_or_36_39 <= and_reduce(match_line(36 to 39)) or pgsize_gte_256M;
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comp_or_34_35 <= and_reduce(match_line(34 to 35)) or pgsize_gte_1G;
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gen_noxbit81 : if have_xbit = 0 generate
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addr_match <= (comp_or_34_35 and -- Ignore functions based on page size
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comp_or_36_39 and
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comp_or_40_43 and
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comp_or_44_45 and
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comp_or_46_47 and
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comp_or_48_49 and
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comp_or_50_51 and
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and_reduce(match_line(31 to 33)) and -- Regular compare largest page size
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(and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn
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not(addr_enable(0)); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_noxbit81;
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gen_xbit81 : if have_xbit /= 0 generate
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addr_match <= (function_50_51 and -- Exclusion functions
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function_48_51 and
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function_46_51 and
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function_44_51 and
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function_40_51 and
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function_36_51 and
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function_34_51 and
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comp_or_34_35 and -- Ignore functions based on page size
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comp_or_36_39 and
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comp_or_40_43 and
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comp_or_44_45 and
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comp_or_46_47 and
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comp_or_48_49 and
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comp_or_50_51 and
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and_reduce(match_line(31 to 33)) and -- Regular compare largest page size
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(and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn
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not(addr_enable(0)); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_xbit81;
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end generate numpgsz8; -- numpgsz8: num_pgsizes = 8
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numpgsz5 : if num_pgsizes = 5 generate
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-- tie off unused signals
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function_50_51 <= '0';
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function_46_51 <= '0';
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function_36_51 <= '0';
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pgsize_eq_16K <= '0';
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pgsize_eq_256K <= '0';
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pgsize_eq_256M <= '0';
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pgsize_gte_16K <= '0';
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pgsize_gte_256K <= '0';
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pgsize_gte_256M <= '0';
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comp_or_34_35 <= '0';
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comp_or_36_39 <= '0';
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comp_or_44_45 <= '0';
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comp_or_46_47 <= '0';
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comp_or_48_49 <= '0';
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comp_or_50_51 <= '0';
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entry_epn_b(34 to 51) <= not(entry_epn(34 to 51));
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gen_nocmpmask50 : if have_cmpmask = 0 generate
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-- 110
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pgsize_eq_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) );
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-- 111
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pgsize_eq_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) );
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-- 101
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pgsize_eq_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2));
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-- 011
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pgsize_eq_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2));
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pgsize_gte_1G <= ( entry_size(0) and entry_size(1) and not(entry_size(2)) );
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pgsize_gte_16M <= ( entry_size(0) and entry_size(1) and entry_size(2) ) or
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pgsize_gte_1G;
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pgsize_gte_1M <= ( entry_size(0) and not(entry_size(1)) and entry_size(2)) or
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pgsize_gte_16M;
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pgsize_gte_64K <= (not(entry_size(0)) and entry_size(1) and entry_size(2)) or
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pgsize_gte_1M;
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end generate gen_nocmpmask50;
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gen_cmpmask50 : if have_cmpmask = 1 generate
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-- size entry_cmpmask: 0123
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-- 1GB 0000
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-- 16MB 1000
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-- 1MB 1100
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-- 64KB 1110
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-- 4KB 1111
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pgsize_gte_1G <= not entry_cmpmask(0);
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pgsize_gte_16M <= not entry_cmpmask(1);
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pgsize_gte_1M <= not entry_cmpmask(2);
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pgsize_gte_64K <= not entry_cmpmask(3);
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-- size entry_xbitmask: 0123
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-- 1GB 1000
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-- 16MB 0100
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-- 1MB 0010
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-- 64KB 0001
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-- 4KB 0000
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pgsize_eq_1G <= entry_xbitmask(0);
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pgsize_eq_16M <= entry_xbitmask(1);
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pgsize_eq_1M <= entry_xbitmask(2);
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pgsize_eq_64K <= entry_xbitmask(3);
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end generate gen_cmpmask50;
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gen_noxbit50 : if have_xbit = 0 generate
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function_34_51 <= '0';
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function_40_51 <= '0';
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function_44_51 <= '0';
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function_48_51 <= '0';
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end generate gen_noxbit50;
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gen_xbit50 : if have_xbit /= 0 generate
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-- 1G
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function_34_51 <= not(entry_xbit) or
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not(pgsize_eq_1G) or
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or_reduce(entry_epn_b(34 to 51) and addr_in(34 to 51));
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-- 16M
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function_40_51 <= not(entry_xbit) or
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not(pgsize_eq_16M) or
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or_reduce(entry_epn_b(40 to 51) and addr_in(40 to 51));
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-- 1M
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function_44_51 <= not(entry_xbit) or
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not(pgsize_eq_1M) or
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or_reduce(entry_epn_b(44 to 51) and addr_in(44 to 51));
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-- 64K
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function_48_51 <= not(entry_xbit) or
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not(pgsize_eq_64K) or
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or_reduce(entry_epn_b(48 to 51) and addr_in(48 to 51));
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end generate gen_xbit50;
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comp_or_48_51 <= and_reduce(match_line(48 to 51)) or pgsize_gte_64K;
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comp_or_44_47 <= and_reduce(match_line(44 to 47)) or pgsize_gte_1M;
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comp_or_40_43 <= and_reduce(match_line(40 to 43)) or pgsize_gte_16M;
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comp_or_34_39 <= and_reduce(match_line(34 to 39)) or pgsize_gte_1G;
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gen_noxbit51 : if have_xbit = 0 generate
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addr_match <= (comp_or_34_39 and -- Ignore functions based on page size
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comp_or_40_43 and
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comp_or_44_47 and
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comp_or_48_51 and
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and_reduce(match_line(31 to 33)) and -- Regular compare largest page size
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(and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn
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not(addr_enable(0)); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_noxbit51;
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gen_xbit51 : if have_xbit /= 0 generate
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addr_match <= (function_48_51 and
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function_44_51 and
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function_40_51 and
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function_34_51 and
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comp_or_34_39 and -- Ignore functions based on page size
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comp_or_40_43 and
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comp_or_44_47 and
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comp_or_48_51 and
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and_reduce(match_line(31 to 33)) and -- Regular compare largest page size
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(and_reduce(match_line(0 to 30)) or not(addr_enable(1)))) or -- ignored part of epn
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not(addr_enable(0)); -- Include address as part of compare,
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-- should never ignore for regular compare/read.
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-- Could ignore for compare/invalidate
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end generate gen_xbit51;
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end generate numpgsz5; -- numpgsz5: num_pgsizes = 5
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pgsize_match <= and_reduce(match_line(52 to 54)) or
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not(pgsize_enable);
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class_match <= (match_line(55) or not(class_enable(0))) and
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(match_line(56) or not(class_enable(1))) and
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(and_reduce(match_line(55 to 56)) or not(class_enable(2)) or
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(not(entry_extclass(1)) and not comp_invalidate)); -- pid_nz bit
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extclass_match <= (match_line(57) or not(extclass_enable(0))) and -- iprot bit
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(match_line(58) or not(extclass_enable(1))); -- pid_nz bit
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state_match <= (match_line(59) or
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not(state_enable(0))) and
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(match_line(60) or
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not(state_enable(1)));
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thdid_match <= (or_reduce(entry_thdid(0 to 3) and comp_thdid(0 to 3)) or not(thdid_enable(0))) and
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(and_reduce(match_line(69 to 72)) or not(thdid_enable(1)) or
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(not(entry_extclass(1)) and not comp_invalidate)); -- pid_nz bit
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pid_match <= and_reduce(match_line(61 to 68)) or
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-- entry_pid=0 ignores pid match for compares,
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|
-- but not for invalidates.
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(not(entry_extclass(1)) and not comp_invalidate) or -- pid_nz bit
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not(pid_enable);
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match <= addr_match and -- Address compare
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pgsize_match and -- Size compare
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class_match and -- Class compare
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extclass_match and -- ExtClass compare
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state_match and -- State compare
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thdid_match and -- ThdID compare
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pid_match and -- PID compare
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|
entry_v; -- Valid
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end tri_cam_32x143_1r1w1c_matchline;
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