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# Testing RTL with new environments
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## Working
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* RTL
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* updated source to remove a bunch of Verilator warnings
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* updated source for compatibility with Icaraus -g2012
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* changed arrays to use clk1x
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* refactored nclk[] to separate clk, rst signals and removed lcb's from clock path
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* Verilator
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* too big(?) to build with verilator --public_flat_rw with cocotb; but --private can override it; see if it finishes
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* executing boot code and tst with a2o_litex wrapper
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* executing boot code and tst with litex-gen'd SOC
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* Icarus (w/cocotb)
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* executing boot code and tst with core/node/a2o_litex
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* Yosys
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* finishes compile
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## Next To Do
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* create Cython code for sharing between cocotb and verilator tb
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* OpenLane experiments with blackbox arrays and yosys/abc/sta
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* create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and *valid* table
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* parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.)
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#### node
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* test BE/LE versions; kernel can stay BE until jump to BIOS; any problem with BIOS to initial ROM copy/zero or is it always words?
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* add L2 internally (before WB); or at least a store queue
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